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  DSP56602 16-bit digital signal processor user? manual motorola, incorporated semiconductor products sector 6501 william cannon drive west austin, tx 78735-8598
this document (and other documents) can be viewed on the world wide web at http://www.motorola-dsp.com. this manual is one of a set of three documents. you need the following manuals to have complete product information: family manual, user? manual, and technical data. once is a trademark of motorola, inc. ? motorola inc. 1997 order this document by DSP56602um/ad motorola reserves the right to make changes without further notice to any products herein to improve reliability, function, or design. motorola does not assume any liability arising out of the application or use of any product or circuit described herein; neither does it convey any license under its patent rights nor the rights of others. motorola products are not authorized for use as components in life support devices or systems intended for surgical implant into the body or intended to support or sustain life. buyer agrees to notify motorola of any such intended end use whereupon motorola shall determine availability and suitability of its product or products for the use intended. motorola and are registered trademarks of motorola, inc. motorola, inc. is an equal employment opportunity /affirmative action employer.
motorola DSP56602 user? manual iii table of contents section 1 DSP56602 overview . . . . . . . . . . . . . . . . . . . . . . . . 1-1 1.1 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-3 1.2 manual conventions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-4 1.3 dsp56600 core description . . . . . . . . . . . . . . . . . . . . . . . 1-6 1.4 dsp56600 core functional blocks . . . . . . . . . . . . . . . . 1-6 1.4.1 data arithmetic logic unit (alu) . . . . . . . . . . . . . . . . . . . . . . 1-7 1.4.1.1 data alu registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-7 1.4.1.2 multiplier-accumulator (mac) . . . . . . . . . . . . . . . . . . . . . . 1-7 1.4.2 address generation unit . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-8 1.4.3 program control unit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-8 1.4.4 program patch logic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-9 1.4.5 pll and clock oscillator . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-10 1.4.6 expansion memory interface (port a) . . . . . . . . . . . . . . . . . 1-10 1.4.7 jtag test access port and on-chip emulation module . . 1-10 1.4.8 on-chip memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-11 1.5 internal buses . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-11 1.6 DSP56602 architecture overview . . . . . . . . . . . . . . . 1-13 1.6.1 gpio functionality. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-13 1.6.2 host interface (hi08) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-13 1.6.3 synchronous serial interface (ssi) . . . . . . . . . . . . . . . . . . . 1-14 1.6.4 triple timer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-14 section 2 signal/connection description . . . . . . . . . . . 2-1 2.1 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-3 2.2 power . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-5 2.3 ground . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-6 2.4 clock and phase lock loop . . . . . . . . . . . . . . . . . . . . . . 2-7 2.5 interrupt and mode control . . . . . . . . . . . . . . . . . . . . 2-8 2.6 external memory interface (port a) . . . . . . . . . . . . 2-10 2.7 host interface (hi08) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-12 2.7.1 host port usage considerations . . . . . . . . . . . . . . . . . . . . . 2-12 2.7.2 host port configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-12
iv DSP56602 user? manual motorola 2.8 synchronous serial interface 0 (ssi0) . . . . . . . . . . .2-18 2.9 synchronous serial interface 1 (ssi1) . . . . . . . . . . .2-21 2.10 general purpose i/o (gpio). . . . . . . . . . . . . . . . . . . . . . .2-24 2.11 triple timer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2-25 2.12 jtag/once interface. . . . . . . . . . . . . . . . . . . . . . . . . . . . .2-26 section 3 memory maps . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3-1 3.1 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3-3 3.2 DSP56602 memory map description . . . . . . . . . . . . . . . .3-3 3.2.1 on-chip program memory . . . . . . . . . . . . . . . . . . . . . . . . . . .3-3 3.2.2 on-chip x data memory. . . . . . . . . . . . . . . . . . . . . . . . . . . . .3-4 3.2.3 on-chip y data memory. . . . . . . . . . . . . . . . . . . . . . . . . . . . .3-4 3.3 memory-mapped i/o registers. . . . . . . . . . . . . . . . . . . . .3-5 section 4 core configuration . . . . . . . . . . . . . . . . . . . . . . .4-1 4.1 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4-3 4.2 dsp56600 core-specific attributes. . . . . . . . . . . . . . . .4-3 4.2.1 program patch detector jump targets . . . . . . . . . . . . . . . . .4-3 4.2.2 operating mode register (omr) . . . . . . . . . . . . . . . . . . . . . .4-4 4.2.2.1 chip operating mode (md?a)?its 0? . . . . . . . . . . . .4-4 4.2.2.2 external bus disable (edb)?it 4 . . . . . . . . . . . . . . . . . .4-5 4.2.2.3 pc relative logic disable (pcd)?it 5 . . . . . . . . . . . . . .4-5 4.2.2.4 stop delay (sd)?it 6. . . . . . . . . . . . . . . . . . . . . . . . . . . .4-5 4.2.2.5 xy select for stack extension (xy)?it 8. . . . . . . . . . . . .4-5 4.2.2.6 extended stack underflow flag (eun)?it 9 . . . . . . . . . .4-5 4.2.2.7 extended stack overflow flag (eov)?it 10 . . . . . . . . . .4-6 4.2.2.8 extended stack wrap flag (wr)?it 11 . . . . . . . . . . . . .4-6 4.2.2.9 extended stack enable (en)?it 12 . . . . . . . . . . . . . . . . .4-6 4.2.2.10 address trace enable (ate)?it 15. . . . . . . . . . . . . . . . .4-6 4.2.2.11 reserved bits?its 7, 13?4 . . . . . . . . . . . . . . . . . . . . . .4-6 4.2.3 status register (sr) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4-7 4.2.4 device identification register (idr) . . . . . . . . . . . . . . . . . . . .4-8 4.2.5 bus control register (bcr) . . . . . . . . . . . . . . . . . . . . . . . . . .4-8 4.3 bootstrap program . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4-8 4.4 chip operating modes . . . . . . . . . . . . . . . . . . . . . . . . . . . .4-9 4.4.1 expanded mode (mode 0). . . . . . . . . . . . . . . . . . . . . . . . . . .4-10
motorola DSP56602 user? manual v 4.4.2 normal mode (modes 1?) . . . . . . . . . . . . . . . . . . . . . . . . . 4-10 4.4.2.1 mode 1?eserved . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-10 4.4.2.2 mode 2?ootstrap from mc68338 . . . . . . . . . . . . . . . . 4-10 4.4.2.3 mode 3?ootstrap from 24-bit memory. . . . . . . . . . . . . 4-10 4.4.2.4 mode 4?ootstrap from 8-bit memory. . . . . . . . . . . . . . 4-10 4.4.2.5 mode 5?ootstrap from isa bus . . . . . . . . . . . . . . . . . . 4-10 4.4.2.6 mode 6?ootstrap from mc68hc11 . . . . . . . . . . . . . . . 4-10 4.4.2.7 mode 7?eserved . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-10 4.5 interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-11 4.5.1 interrupt priority levels . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-13 4.5.2 interrupt sources priorities within an ipl. . . . . . . . . . . . . . . 4-15 4.6 phase lock loop . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-16 4.6.1 pll control register 0 (pctl0) . . . . . . . . . . . . . . . . . . . . . 4-17 4.6.1.1 multiplication factor bits (mf[11:0])?its 0?1 . . . . . . . 4-17 4.6.1.2 predivider factor bits (pd[3:0])?its 12?5 . . . . . . . . . 4-17 4.6.2 pll control register 1 (pctl1) . . . . . . . . . . . . . . . . . . . . . 4-18 4.6.2.1 division factor (df[2:0])?its 0?. . . . . . . . . . . . . . . . . 4-18 4.6.2.2 crystal range (xtlr)?it 3 . . . . . . . . . . . . . . . . . . . . . 4-19 4.6.2.3 crystal disable (xtld)?it 4. . . . . . . . . . . . . . . . . . . . . 4-19 4.6.2.4 stop processing state (pstp)?it 5. . . . . . . . . . . . . . . . 4-19 4.6.2.5 pll enable (pen)?it 6 . . . . . . . . . . . . . . . . . . . . . . . . 4-19 4.6.2.6 clock output disable (cod)?it 7 . . . . . . . . . . . . . . . . 4-19 4.6.2.7 predivider factor (pd[6:4])?its 9?1. . . . . . . . . . . . . . 4-20 4.6.2.8 reserved bits?its 8, 12?5 . . . . . . . . . . . . . . . . . . . . . 4-20 section 5 external memory interface (port a) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-1 5.1 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-3 5.2 port a signal description . . . . . . . . . . . . . . . . . . . . . . . 5-3 5.2.1 address bus (a0?15) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-3 5.2.2 data bus (d0?23) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-3 5.2.3 memory chip select (mcs ) . . . . . . . . . . . . . . . . . . . . . . . . . . 5-3 5.2.4 read enable (rd ) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-4 5.2.5 write enable (wr ) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-4 5.2.6 address trace (at ) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-4 5.3 port a operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-4
vi DSP56602 user? manual motorola 5.3.1 static ram support. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .5-4 5.3.2 disabling port a . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .5-7 5.4 port a control and data transfer . . . . . . . . . . . . . . .5-7 5.4.1 bus control register (bcr) . . . . . . . . . . . . . . . . . . . . . . . . . .5-7 5.4.1.1 expansion bus memory wait (bmw[4:0])?its 0? . . . . .5-7 5.4.1.2 reserved bits?its 5?5 . . . . . . . . . . . . . . . . . . . . . . . . .5-8 5.4.2 bus switch program memory register (bpmr) . . . . . . . . . . .5-8 5.4.2.1 bpmr mapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .5-8 5.4.2.2 24-bit access to bpmr . . . . . . . . . . . . . . . . . . . . . . . . . . .5-9 5.4.2.3 16-bit access to bpmr . . . . . . . . . . . . . . . . . . . . . . . . . . .5-9 5.4.2.4 bpmr usage typical examples . . . . . . . . . . . . . . . . . . . .5-9 5.5 program address tracing mode. . . . . . . . . . . . . . . . .5-10 section 6 gpio . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .6-1 6.1 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .6-3 6.2 gpio configuration. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .6-3 6.3 gpio port e control register (pcre) . . . . . . . . . . . . .6-5 6.4 gpio port e direction register (prre) . . . . . . . . . . . .6-5 6.5 gpio port e data register (pdre) . . . . . . . . . . . . . . . . .6-6 section 7 host interface (hi08) . . . . . . . . . . . . . . . . . . . . . .7-1 7.1 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .7-3 7.2 interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .7-3 7.2.1 dsp side. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .7-3 7.2.2 host side. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .7-4 7.3 hi08 host port . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .7-6 7.4 host interface?sp programmer? model . . . . . . .7-7 7.4.1 hi08 control register (hcr) . . . . . . . . . . . . . . . . . . . . . . . . .7-8 7.4.1.1 host receive interrupt enable (hrie)?it 0. . . . . . . . . . .7-9 7.4.1.2 host transmit interrupt enable (htie)?it 1 . . . . . . . . . .7-9 7.4.1.3 host command interrupt enable (hcie)?it 2 . . . . . . . . .7-9 7.4.1.4 host flags 2 and 3 (hf[3:2])?its 3? . . . . . . . . . . . . . .7-10 7.4.1.5 reserved bits?its 5?5 . . . . . . . . . . . . . . . . . . . . . . . .7-10 7.4.2 hi08 status register (hsr) . . . . . . . . . . . . . . . . . . . . . . . . .7-10 7.4.2.1 host receive data full (hrdf)?it 0 . . . . . . . . . . . . . .7-10 7.4.2.2 host transmit data empty (htde)?it 1 . . . . . . . . . . . .7-11
motorola DSP56602 user? manual vii 7.4.2.3 host command pending (hcp)?it 2 . . . . . . . . . . . . . . 7-11 7.4.2.4 host flags 0 and 1 (hf[1:0])?its 3? . . . . . . . . . . . . . 7-11 7.4.2.5 reserved bits?its 5?5 . . . . . . . . . . . . . . . . . . . . . . . . 7-11 7.4.3 hi08 port control register (hpcr) . . . . . . . . . . . . . . . . . . . 7-12 7.4.3.1 host gpio port enable (hgen)?it 0 . . . . . . . . . . . . . 7-12 7.4.3.2 host address line 8 enable (ha8en)?it 1 . . . . . . . . . 7-12 7.4.3.3 host address line 9 enable (ha9en)?it 2 . . . . . . . . . 7-12 7.4.3.4 host chip select enable (hcsen)?it 3 . . . . . . . . . . . 7-13 7.4.3.5 host request enable (hren)?it 4 . . . . . . . . . . . . . . . 7-13 7.4.3.6 host acknowledge enable (haen)?it 5 . . . . . . . . . . . 7-13 7.4.3.7 host enable (hen)?it 6. . . . . . . . . . . . . . . . . . . . . . . . 7-13 7.4.3.8 reserved bit?it 7. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-13 7.4.3.9 host request open drain (hrod)?it 8 . . . . . . . . . . . 7-13 7.4.3.10 host data strobe polarity (hdsp)?it 9 . . . . . . . . . . . . 7-14 7.4.3.11 host address strobe polarity (hasp)?it 10 . . . . . . . . 7-14 7.4.3.12 host multiplexed bus (hmux)?it 11 . . . . . . . . . . . . . . 7-14 7.4.3.13 host dual data strobe (hdds)?it 12 . . . . . . . . . . . . . 7-14 7.4.3.14 host chip select polarity (hcsp)?it 13 . . . . . . . . . . . 7-15 7.4.3.15 host request polarity (hrp)?it 14 . . . . . . . . . . . . . . . 7-15 7.4.3.16 host acknowledge polarity (hap)?it 15 . . . . . . . . . . . 7-16 7.4.4 hi08 data direction register (hddr) . . . . . . . . . . . . . . . . . 7-16 7.4.5 hi08 data register (hdr) . . . . . . . . . . . . . . . . . . . . . . . . . . 7-16 7.4.6 hi08 base address register (hbar) . . . . . . . . . . . . . . . . . 7-17 7.4.7 hi08 receive data register (hrx) . . . . . . . . . . . . . . . . . . . 7-18 7.4.8 hi08 transmit data register (htx). . . . . . . . . . . . . . . . . . . 7-18 7.4.9 dsp side registers after reset . . . . . . . . . . . . . . . . . . . . . 7-19 7.4.10 hi08 dsp core interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . 7-19 7.5 hi08?xternal host programmer? model . . . . . . 7-20 7.5.1 interface control register (icr) . . . . . . . . . . . . . . . . . . . . . 7-22 7.5.1.1 receive request enable (rreq)?it 0 . . . . . . . . . . . . 7-23 7.5.1.2 transmit request enable (treq)?it 1 . . . . . . . . . . . . . 7-23 7.5.1.3 double host request (hdrq)?it 2 . . . . . . . . . . . . . . . 7-24 7.5.1.4 host flag 0 (hf0)?it 3. . . . . . . . . . . . . . . . . . . . . . . . . 7-24 7.5.1.5 host flag 1 (hf1)?it 4. . . . . . . . . . . . . . . . . . . . . . . . . 7-24 7.5.1.6 host little endian (hlend)?it 5 . . . . . . . . . . . . . . . . . 7-24 7.5.1.7 initialize bit (init)?it 7 . . . . . . . . . . . . . . . . . . . . . . . . . 7-24
viii DSP56602 user? manual motorola 7.5.1.8 reserved bit?it 6 . . . . . . . . . . . . . . . . . . . . . . . . . . . . .7-25 7.5.2 command vector register (cvr). . . . . . . . . . . . . . . . . . . . .7-25 7.5.2.1 host vector (hv[6:0])?its 0?. . . . . . . . . . . . . . . . . . . .7-25 7.5.2.2 host command bit (hc)?it 7 . . . . . . . . . . . . . . . . . . . .7-26 7.5.3 interface status register (isr) . . . . . . . . . . . . . . . . . . . . . . .7-26 7.5.3.1 receive data register full (rxdf)?it 0. . . . . . . . . . . .7-26 7.5.3.2 transmit data register empty (txde)?it 1 . . . . . . . . .7-27 7.5.3.3 transmitter ready (trdy)?it 2 . . . . . . . . . . . . . . . . . .7-27 7.5.3.4 host flag 2 (hf2)?it 3 . . . . . . . . . . . . . . . . . . . . . . . . .7-27 7.5.3.5 host flag 3 (hf3)?it 4 . . . . . . . . . . . . . . . . . . . . . . . . . .7-27 7.5.3.6 reserved bits?its 5 and 6 . . . . . . . . . . . . . . . . . . . . . .7-27 7.5.3.7 isr host request (hreq)?it 7 . . . . . . . . . . . . . . . . . .7-27 7.5.4 interrupt vector register (ivr) . . . . . . . . . . . . . . . . . . . . . . .7-28 7.5.5 receive byte registers (rxh, rxl). . . . . . . . . . . . . . . . . . .7-28 7.5.6 transmit byte registers (txh, txl). . . . . . . . . . . . . . . . . . .7-29 7.5.7 host side registers after reset . . . . . . . . . . . . . . . . . . . . . .7-29 7.6 general purpose i/o . . . . . . . . . . . . . . . . . . . . . . . . . . . . .7-30 7.6.1 servicing the host interface . . . . . . . . . . . . . . . . . . . . . . . . .7-31 7.6.2 hi08 host processor data transfer . . . . . . . . . . . . . . . . . . .7-31 7.6.3 polling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .7-31 7.6.4 servicing interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .7-32 section 8 synchronous serial interface. . . . . . . . . . . .8-1 8.1 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .8-3 8.2 ssi data and control pins . . . . . . . . . . . . . . . . . . . . . . . .8-4 8.2.1 serial control 0 (sc0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .8-4 8.2.2 serial control 1 (sc1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .8-4 8.2.3 serial control 2 (sc2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .8-5 8.2.4 serial clock (sck) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .8-5 8.2.5 serial receive data (srd) . . . . . . . . . . . . . . . . . . . . . . . . . . .8-6 8.2.6 serial transmit data (std). . . . . . . . . . . . . . . . . . . . . . . . . . .8-6 8.3 ssi programming model . . . . . . . . . . . . . . . . . . . . . . . . . .8-7 8.3.1 ssi control register a (cra) . . . . . . . . . . . . . . . . . . . . . . . . .8-7 8.3.1.1 prescale modulus select (pm[7:0])?its 0? . . . . . . . . . .8-8 8.3.1.2 frame rate divider control (dc[4:0])?its 8?2 . . . . . . .8-8 8.3.1.3 word length control (wl[1:0])?its 13?4 . . . . . . . . . . .8-8
motorola DSP56602 user? manual ix 8.3.1.4 prescaler range (psr)?it 15 . . . . . . . . . . . . . . . . . . . . 8-9 8.3.2 ssi control register b (crb) . . . . . . . . . . . . . . . . . . . . . . . . 8-9 8.3.2.1 serial output flag 0 (of0)?it 0 . . . . . . . . . . . . . . . . . . 8-10 8.3.2.2 serial output flag 1 (of1)?it 1 . . . . . . . . . . . . . . . . . . 8-10 8.3.2.3 reserved bits?its 2? . . . . . . . . . . . . . . . . . . . . . . . . . 8-10 8.3.2.4 transmit enable (te)?it 8 . . . . . . . . . . . . . . . . . . . . . . 8-11 8.3.2.5 receive enable (re)?it 9 . . . . . . . . . . . . . . . . . . . . . . 8-12 8.3.2.6 transmit interrupt enable (tie)?it 10 . . . . . . . . . . . . . 8-12 8.3.2.7 receive interrupt enable (rie)?it 11 . . . . . . . . . . . . . 8-12 8.3.2.8 transmit last slot interrupt enable (tlie)?it 12. . . . . 8-13 8.3.2.9 receive last slot interrupt enable (rlie)?it 13 . . . . . 8-13 8.3.2.10 transmit exception interrupt enable (teie)?it 14. . . . 8-13 8.3.2.11 receive exception interrupt enable (reie)?it 15 . . . . 8-13 8.3.3 ssi control register c (crc) . . . . . . . . . . . . . . . . . . . . . . . 8-13 8.3.3.1 asynchronous /synchronous (syn)?it 0. . . . . . . . . . . 8-14 8.3.3.2 ssi mode select (mod)?it 1. . . . . . . . . . . . . . . . . . . . 8-14 8.3.3.3 serial control 0 direction (scd0)?it 2 . . . . . . . . . . . . 8-14 8.3.3.4 serial control 1 direction (scd1)?it 3 . . . . . . . . . . . . 8-14 8.3.3.5 serial control 2 direction (scd2)?it 4 . . . . . . . . . . . . 8-15 8.3.3.6 clock source direction (sckd)?it 5 . . . . . . . . . . . . . . 8-15 8.3.3.7 clock polarity (ckp)?it 6. . . . . . . . . . . . . . . . . . . . . . . 8-15 8.3.3.8 shift direction (shfd)?it 7 . . . . . . . . . . . . . . . . . . . . . 8-15 8.3.3.9 reserved bits?its 8?1 . . . . . . . . . . . . . . . . . . . . . . . . 8-15 8.3.3.10 frame sync length (fsl[1:0])?its 12?3 . . . . . . . . . . 8-15 8.3.3.11 frame sync relative timing (fsr)?it 14 . . . . . . . . . . 8-16 8.3.3.12 frame sync polarity (fsp)?it 15. . . . . . . . . . . . . . . . . 8-16 8.3.4 ssi status register (ssisr) . . . . . . . . . . . . . . . . . . . . . . . . 8-16 8.3.4.1 serial input flag 0 (if0)?it 0 . . . . . . . . . . . . . . . . . . . . 8-17 8.3.4.2 serial input flag 1 (if1)?it 1 . . . . . . . . . . . . . . . . . . . . 8-17 8.3.4.3 transmit frame sync flag (tfs)?it 2. . . . . . . . . . . . . 8-17 8.3.4.4 receive frame sync flag (rfs)?it 3 . . . . . . . . . . . . . 8-17 8.3.4.5 transmitter underrun error flag (tue)?it 4 . . . . . . . . 8-18 8.3.4.6 receiver overrun error flag (roe)?it 5 . . . . . . . . . . . 8-18 8.3.4.7 transmit data register empty (tde)?it 6. . . . . . . . . . 8-18 8.3.4.8 receive data register full (rdf)?it 7 . . . . . . . . . . . . 8-18 8.3.4.9 reserved bits?its 8?5 . . . . . . . . . . . . . . . . . . . . . . . . 8-19
x DSP56602 user? manual motorola 8.3.5 receive shift register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . .8-19 8.3.6 receive data register (rx) . . . . . . . . . . . . . . . . . . . . . . . . .8-19 8.3.7 transmit shift register . . . . . . . . . . . . . . . . . . . . . . . . . . . . .8-19 8.3.8 transmit data register (tx) . . . . . . . . . . . . . . . . . . . . . . . . .8-20 8.3.9 time slot register (tsr) . . . . . . . . . . . . . . . . . . . . . . . . . . .8-20 8.3.10 port control register (pcr) . . . . . . . . . . . . . . . . . . . . . . . . .8-20 8.3.10.1 port control (pc[5:0])?its 0? . . . . . . . . . . . . . . . . . . .8-20 8.3.10.2 port enable (pen)?it 7 . . . . . . . . . . . . . . . . . . . . . . . . .8-21 8.3.10.3 reserved bits?its 6, 8?5 . . . . . . . . . . . . . . . . . . . . . .8-21 8.3.11 port direction register (prr) . . . . . . . . . . . . . . . . . . . . . . . .8-21 8.3.12 port data register (pdr) . . . . . . . . . . . . . . . . . . . . . . . . . . .8-22 8.4 operating modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .8-22 8.4.1 ssi exceptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .8-23 8.4.2 operating modes?ormal, network, and on-demand . . . . .8-24 8.4.2.1 operating mode selection . . . . . . . . . . . . . . . . . . . . . . . .8-24 8.4.2.2 synchronous/asynchronous operating modes . . . . . . . .8-24 8.4.2.3 frame sync selection . . . . . . . . . . . . . . . . . . . . . . . . . . .8-25 8.4.2.4 shift direction selection . . . . . . . . . . . . . . . . . . . . . . . . . .8-26 8.4.3 serial i/o flags . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .8-26 section 9 triple timer module . . . . . . . . . . . . . . . . . . . . . . .9-1 9.1 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .9-3 9.2 triple timer module architecture . . . . . . . . . . . . . . .9-3 9.3 timer architecture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .9-4 9.4 triple timer module programming model. . . . . . . . .9-6 9.4.1 timer prescaler load register (tplr). . . . . . . . . . . . . . . . . .9-7 9.4.1.1 prescaler preload value (pl[13:0])?its 0?3 . . . . . . . . .9-7 9.4.1.2 prescaler source (ps[1:0])?its 14?5 . . . . . . . . . . . . . .9-7 9.4.2 timer prescaler count register (tpcr). . . . . . . . . . . . . . . . .9-8 9.4.2.1 prescaler counter value (pc[13:0])?its 0?3 . . . . . . . .9-8 9.4.2.2 reserved bits?its 14?5 . . . . . . . . . . . . . . . . . . . . . . . .9-8 9.4.3 timer count register (tcr) . . . . . . . . . . . . . . . . . . . . . . . . . .9-8 9.4.4 timer load register (tlr) . . . . . . . . . . . . . . . . . . . . . . . . . . .9-8 9.4.5 timer compare register (tcpr) . . . . . . . . . . . . . . . . . . . . . .9-9 9.4.6 timer control/status register (tcsr) . . . . . . . . . . . . . . . . . .9-9 9.4.6.1 timer enable (te)?it 0 . . . . . . . . . . . . . . . . . . . . . . . . . .9-9
motorola DSP56602 user? manual xi 9.4.6.2 timer overflow interrupt enable (toie)?it 1. . . . . . . . . 9-9 9.4.6.3 timer compare interrupt enable (tcie)?it 2 . . . . . . . . . 9-9 9.4.6.4 timer control (tc[3:0])?its 4?. . . . . . . . . . . . . . . . . . 9-10 9.4.6.5 inverter (inv)?it 8 . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-11 9.4.6.6 timer reload mode (trm)?it 9. . . . . . . . . . . . . . . . . . 9-11 9.4.6.7 direction (dir)?it 10 . . . . . . . . . . . . . . . . . . . . . . . . . . 9-11 9.4.6.8 data input (di)?it 11 . . . . . . . . . . . . . . . . . . . . . . . . . . 9-11 9.4.6.9 data output (do)?it 12 . . . . . . . . . . . . . . . . . . . . . . . . 9-12 9.4.6.10 timer overflow flag (tof)?it 13 . . . . . . . . . . . . . . . . 9-12 9.4.6.11 timer compare flag (tcf)?it 14 . . . . . . . . . . . . . . . . 9-12 9.4.6.12 prescaled clock enable (pce)?it 15 . . . . . . . . . . . . . 9-12 9.4.6.13 reserved bit?it 3. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-13 9.5 timer modes of operation . . . . . . . . . . . . . . . . . . . . . . 9-13 9.5.1 timer modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-14 9.5.1.1 mode 0?imer, no output (internal clock) . . . . . . . . . . 9-14 9.5.1.2 mode 1?imer, output pulse (internal clock) . . . . . . . . 9-14 9.5.1.3 mode 2?imer, output toggle (internal clock) . . . . . . . 9-15 9.5.1.4 mode 3?imer, event counter (external clock) . . . . . . 9-15 9.5.2 measurement modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-16 9.5.2.1 mode 4?ulse width measurement . . . . . . . . . . . . . . . 9-16 9.5.2.2 mode 5?eriod measurement . . . . . . . . . . . . . . . . . . . . 9-16 9.5.2.3 mode 6?apture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-17 9.5.3 pulse width modulation mode . . . . . . . . . . . . . . . . . . . . . . . 9-17 9.5.3.1 mode 7?wm, output toggle (internal clock) . . . . . . . 9-17 9.5.4 watchdog modes. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-18 9.5.4.1 mode 9?atchdog, output pulse (internal clock) . . . . 9-18 9.5.4.2 mode 10?atchdog, output toggle (internal clock) . . 9-18 9.5.5 reserved modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-19 9.5.6 timer behavior during wait and stop instructions . . . . . 9-19 section 10 on-chip emulation module . . . . . . . . . . . . . . . 10-1 10.1 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-3 10.2 once module pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-3 10.3 once controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-4 10.3.1 once command register (ocr) . . . . . . . . . . . . . . . . . . . . 10-5 10.3.1.1 register select (rs[4:0])?its 0? . . . . . . . . . . . . . . . . 10-5
xii DSP56602 user? manual motorola 10.3.1.2 exit command (ex)?it 5 . . . . . . . . . . . . . . . . . . . . . . . .10-7 10.3.1.3 go command (go)?it 6 . . . . . . . . . . . . . . . . . . . . . . .10-7 10.3.1.4 read/write command (r/w )?it 7. . . . . . . . . . . . . . . . .10-7 10.3.2 once decoder (odec) . . . . . . . . . . . . . . . . . . . . . . . . . . . .10-8 10.3.3 once status and control register (oscr) . . . . . . . . . . . . .10-8 10.3.3.1 trace mode enable (tme)?it 0 . . . . . . . . . . . . . . . . . .10-8 10.3.3.2 interrupt mode enable (ime)?it 1 . . . . . . . . . . . . . . . . .10-8 10.3.3.3 software debug occurrence (swo)?it 2 . . . . . . . . . . .10-8 10.3.3.4 memory breakpoint occurrence (mbo)?it 3 . . . . . . . .10-9 10.3.3.5 trace occurrence (to)?it 4 . . . . . . . . . . . . . . . . . . . . .10-9 10.3.3.6 reserved bit?it 5 . . . . . . . . . . . . . . . . . . . . . . . . . . . . .10-9 10.3.3.7 core status (os[1:0])?its 6-7 . . . . . . . . . . . . . . . . . . . .10-9 10.3.3.8 reserved bits?its 8?3 . . . . . . . . . . . . . . . . . . . . . . . .10-9 10.4 once memory breakpoint logic. . . . . . . . . . . . . . . . .10-10 10.4.1 once memory address latch (omal). . . . . . . . . . . . . . . .10-11 10.4.2 once memory limit register 0 (omlr0). . . . . . . . . . . . . .10-11 10.4.3 once memory address comparator 0 (omac0) . . . . . . . .10-11 10.4.4 once memory limit register 1 (omlr1). . . . . . . . . . . . . .10-11 10.4.5 once memory address comparator 1 (omac1) . . . . . . . .10-11 10.4.6 once breakpoint control register (obcr) . . . . . . . . . . . .10-12 10.4.6.1 memory breakpoint select bits (mbs[1:0])?its 0? . .10-12 10.4.6.2 breakpoint0 read/write select (rw0[1:0])?its 2? . .10-12 10.4.6.3 breakpoint0 cc select (cc0[1:0])?its 4? . . . . . . . . .10-13 10.4.6.4 breakpoint1 read/write select (rw1[1:0])?its 6? . .10-13 10.4.6.5 breakpoint1 cc select (cc1[1:0])?its 8? . . . . . . . . .10-14 10.4.6.6 breakpoint event select bits (bt[1:0])?its 10?1 . . .10-14 10.4.6.7 reserved bits?its 12?5 . . . . . . . . . . . . . . . . . . . . . .10-14 10.4.7 once memory breakpoint counter (ombc) . . . . . . . . . . .10-14 10.5 once trace logic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .10-15 10.6 methods of entering the debug mode . . . . . . . . . .10-16 10.6.1 external debug request during reset assertion . . . . . .10-16 10.6.2 external debug request during normal activity . . . . . . . .10-17 10.6.3 executing the jtag debug_request instruction . . . . .10-17 10.6.4 external debug request during stop mode . . . . . . . . . . . .10-17 10.6.5 external debug request during wait mode . . . . . . . . . . . .10-17 10.6.6 software request during normal activity . . . . . . . . . . . . . .10-18
motorola DSP56602 user? manual xiii 10.6.7 enabling trace mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-18 10.6.8 enabling memory breakpoints. . . . . . . . . . . . . . . . . . . . . . 10-18 10.7 pipeline information and ogdbr . . . . . . . . . . . . . . . 10-18 10.7.1 once pdb register (opdbr) . . . . . . . . . . . . . . . . . . . . . 10-19 10.7.2 once pil register (opilr) . . . . . . . . . . . . . . . . . . . . . . . 10-19 10.7.3 once gdb register (ogdbr) . . . . . . . . . . . . . . . . . . . . . 10-20 10.8 trace buffer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-20 10.8.1 once pab register for fetch (opabfr) . . . . . . . . . . . . . 10-20 10.8.2 pab register for decode (opabdr) . . . . . . . . . . . . . . . . 10-20 10.8.3 once pab register for execute (opabex) . . . . . . . . . . . 10-21 10.8.4 trace buffer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-21 10.9 once commands and serial protocol . . . . . . . . . . 10-23 10.10 target site debug system requirements . . . . . . 10-24 10.11 examples of using the once . . . . . . . . . . . . . . . . . . . 10-24 10.11.1 checking whether the chip has entered the debug mode 10-24 10.11.2 polling the jtag instruction shift register . . . . . . . . . . . . 10-25 10.11.3 saving pipeline information . . . . . . . . . . . . . . . . . . . . . . . . 10-25 10.11.4 reading the trace buffer. . . . . . . . . . . . . . . . . . . . . . . . . . 10-25 10.11.5 displaying a specified register . . . . . . . . . . . . . . . . . . . . . 10-26 10.11.6 displaying x memory area starting at address $xxxx . . . 10-27 10.11.7 going from debug to normal mode in a current program 10-28 10.11.8 going from debug to normal mode in a new program . . . 10-28 10.12 examples of jtag and once interaction . . . . . . . 10-29 section 11 jtag port . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-1 11.1 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-3 11.2 jtag pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-5 11.2.1 test clock (tck) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-5 11.2.2 test mode select (tms) . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-5 11.2.3 test data input (tdi) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-5 11.2.4 test data output (tdo) . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-5 11.2.5 test reset (trst ). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-5 11.3 tap controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-6 11.3.1 boundary scan register . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-7 11.3.2 instruction register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-7 11.3.2.1 extest (b[3:0] = 0000) . . . . . . . . . . . . . . . . . . . . . . . . . 11-9
xiv DSP56602 user? manual motorola 11.3.2.2 sample/preload (b[3:0] = 0001) . . . . . . . . . . . . . . . .11-9 11.3.2.3 idcode (b[3:0] = 0010). . . . . . . . . . . . . . . . . . . . . . . . . .11-9 11.3.2.4 clamp (b[3:0] = 0011) . . . . . . . . . . . . . . . . . . . . . . . . .11-10 11.3.2.5 hi-z (b[3:0] = 0100) . . . . . . . . . . . . . . . . . . . . . . . . . . . .11-11 11.3.2.6 enable_once(b[3:0] = 0110) . . . . . . . . . . . . . . . . . . .11-11 11.3.2.7 debug_request(b[3:0] = 0111) . . . . . . . . . . . . . . . .11-11 11.3.2.8 bypass (b[3:0] = 1111) . . . . . . . . . . . . . . . . . . . . . . . .11-12 11.4 dsp56600 restrictions . . . . . . . . . . . . . . . . . . . . . . . . . .11-12 appendix a bootstrap program . . . . . . . . . . . . . . . . . . . . . a-1 a.1 DSP56602 bootstrap listing . . . . . . . . . . . . . . . . . . . . . . a-3 appendix b x i/o equates . . . . . . . . . . . . . . . . . . . . . . . . . . . . . b-1 b.1 DSP56602 x i/o equates . . . . . . . . . . . . . . . . . . . . . . . . . . . b-3 b.2 DSP56602 interrupt equates . . . . . . . . . . . . . . . . . . . . b-10 appendix c bsdl listing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . c-1 c.1 DSP56602 bsdl listing . . . . . . . . . . . . . . . . . . . . . . . . . . . . c-3 appendix d programmer? reference . . . . . . . . . . . . . . . . d-1 d.1 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . d-3 d.2 instruction set summary. . . . . . . . . . . . . . . . . . . . . . . . d-3 d.3 interrupt, vector, and address tables . . . . . . . . d-14 d.4 programmer? sheets . . . . . . . . . . . . . . . . . . . . . . . . . . d-23
motorola DSP56602 user? manual xv list of figures figure 1-1 DSP56602 block diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-12 figure 2-1 DSP56602 signals identified by functional group . . . . . . . . . . . . . . 2-4 figure 3-1 DSP56602 memory map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-3 figure 4-1 operating mode register (omr) programming model . . . . . . . . . . . 4-4 figure 4-2 status register programming model. . . . . . . . . . . . . . . . . . . . . . . . . 4-7 figure 4-3 DSP56602 device id register (idr). . . . . . . . . . . . . . . . . . . . . . . . . 4-8 figure 4-4 interrupt priority registers ipr-c and ipr-p . . . . . . . . . . . . . . . . . 4-14 figure 4-5 pll control register 0 (pctl0) programming model . . . . . . . . . . 4-17 figure 4-6 pll control register 1 (pctl1) programming model . . . . . . . . . . 4-18 figure 5-1 static ram connection diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-5 figure 5-2 bus operation, one wait state?ram access. . . . . . . . . . . . . . . . 5-6 figure 5-3 bus control register (bcr) programming model . . . . . . . . . . . . . . . 5-7 figure 5-4 bpmr register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-9 figure 5-5 possible address tracing configuration diagram. . . . . . . . . . . . . . 5-11 figure 6-1 gpio port e programming model . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-4 figure 7-1 hi08 block diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-7 figure 7-2 host control register programming model. . . . . . . . . . . . . . . . . . . . 7-9 figure 7-3 host status register (hsr) programming model . . . . . . . . . . . . . . 7-10 figure 7-4 host port control register (hpcr) programming model . . . . . . . . 7-12
xvi DSP56602 user? manual motorola figure 7-5 single and dual strobe bus modes . . . . . . . . . . . . . . . . . . . . . . . . . 7-15 figure 7-6 host data direction register (hddr) programming model. . . . . . . 7-16 figure 7-7 host data register (hdr) programming model . . . . . . . . . . . . . . . 7-16 figure 7-8 self chip select logic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-17 figure 7-9 host base address register (hbar) programming model . . . . . . . 7-18 figure 7-10 hsr?cr operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-20 figure 7-11 interface control register programming model . . . . . . . . . . . . . . . . 7-22 figure 7-12 command vector register (cvr) . . . . . . . . . . . . . . . . . . . . . . . . . . 7-25 figure 7-13 interface status register programming model . . . . . . . . . . . . . . . . 7-26 figure 7-14 interrupt vector register (ivr). . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-28 figure 7-15 hi08 host request structure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-32 figure 8-1 ssi block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-3 figure 8-2 ssi control register a programming model . . . . . . . . . . . . . . . . . . . 8-8 figure 8-3 ssi control register b programming model . . . . . . . . . . . . . . . . . . 8-10 figure 8-4 ssi control register c programming model . . . . . . . . . . . . . . . . . . 8-14 figure 8-5 ssi status register programming model. . . . . . . . . . . . . . . . . . . . . 8-16 figure 8-6 ssi port control register programming model . . . . . . . . . . . . . . . . 8-20 figure 8-7 ssi gpio direction control register programming model . . . . . . . 8-21 figure 8-8 ssi gpio data register programming model . . . . . . . . . . . . . . . . . 8-22 figure 9-1 triple timer module block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . 9-4 figure 9-2 16-bit timer module block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . 9-5 figure 9-3 triple timers programming model . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-6
motorola DSP56602 user? manual xvii figure 10-1 once module block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-3 figure 10-2 once module multiprocessor configuration . . . . . . . . . . . . . . . . . . 10-4 figure 10-3 once controller block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-5 figure 10-4 once command register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-5 figure 10-5 once status and control register (oscr) . . . . . . . . . . . . . . . . . . 10-8 figure 10-6 once memory breakpoint logic 0 . . . . . . . . . . . . . . . . . . . . . . . . 10-10 figure 10-7 once breakpoint control register (obcr) . . . . . . . . . . . . . . . . . 10-12 figure 10-8 once trace logic block diagram. . . . . . . . . . . . . . . . . . . . . . . . . 10-15 figure 10-9 once pipeline information and gdb registers . . . . . . . . . . . . . . 10-19 figure 10-10 once trace buffer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-22 figure 11-1 tap block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-4 figure 11-2 tap controller state machine . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-6 figure 11-3 jtag instruction register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-7 figure 11-4 jtag id register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-10 figure 11-5 bypass register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-12
xviii DSP56602 user? manual motorola
motorola DSP56602 user? manual xix list of tables table 1-1 high true / low true signal conventions. . . . . . . . . . . . . . . . . . . . . 1-5 table 2-1 functional group signal allocations . . . . . . . . . . . . . . . . . . . . . . . . . 2-3 table 2-2 power inputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-5 table 2-3 grounds. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-6 table 2-4 clock and pll signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-7 table 2-5 interrupt and mode control signals. . . . . . . . . . . . . . . . . . . . . . . . . . 2-8 table 2-6 external memory interface (port a) signals . . . . . . . . . . . . . . . . . . 2-10 table 2-7 host port usage considerations . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-12 table 2-8 host interface signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-13 table 2-9 synchronous serial interface 0 (ssi0) . . . . . . . . . . . . . . . . . . . . . . 2-18 table 2-10 synchronous serial interface 1 (ssi1) . . . . . . . . . . . . . . . . . . . . . . 2-21 table 2-11 general purpose i/o (gpio) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-24 table 2-12 triple timer signals. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-25 table 2-13 jtag interface/on-chip emulation module (once) signals . . . . . 2-26 table 3-1 internal i/o memory map. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-5 table 4-1 patch jump targets . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-4 table 4-2 DSP56602 reset addresses. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-9 table 4-3 interrupt sources . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-11 table 4-4 interrupt priority level bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-14
xx DSP56602 user? manual motorola table 4-5 external interrupt trigger mode bits . . . . . . . . . . . . . . . . . . . . . . . . 4-14 table 4-6 interrupt source priorities within an ipl . . . . . . . . . . . . . . . . . . . . . . 4-15 table 4-7 multiplication factor bits mf[11:0] . . . . . . . . . . . . . . . . . . . . . . . . . . 4-17 table 4-8 division factor bits. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-18 table 6-1 pcre and prre bits functionality . . . . . . . . . . . . . . . . . . . . . . . . . . 6-5 table 7-1 summary of hi08 pins and operating modes . . . . . . . . . . . . . . . . . . 7-6 table 7-2 strobe signals support pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-6 table 7-3 host request support pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-6 table 7-4 hi08 interrupt request priority order. . . . . . . . . . . . . . . . . . . . . . . . . 7-9 table 7-5 hdr and hddr bits functionality . . . . . . . . . . . . . . . . . . . . . . . . . . 7-17 table 7-6 dsp side registers after reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-19 table 7-7 hi08 host side register map. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-22 table 7-8 treq and hreq modes (hdrq = 0) . . . . . . . . . . . . . . . . . . . . . . . 7-23 table 7-9 treq and hreq modes (hdrq = 1) . . . . . . . . . . . . . . . . . . . . . . . 7-23 table 7-10 init commands . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-25 table 7-11 host side registers after reset. . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-30 table 8-1 ssi clock sources . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-6 table 8-2 ssi word length selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-9 table 8-3 mode and pin definition table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-11 table 8-4 fsl[1:0] encoding . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-16 table 8-5 pcr and prr register bits functionality . . . . . . . . . . . . . . . . . . . . 8-21 table 9-1 ps[1:0] bit functionality . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-7
motorola DSP56602 user? manual xxi table 9-2 tc[3:0] bit functionality . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-10 table 9-3 timer mode summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-13 table 10-1 once register select encoding . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-6 table 10-2 ex bit definition. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-7 table 10-3 go bit definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-7 table 10-4 r/w bit definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-7 table 10-5 core status bits description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-9 table 10-6 memory breakpoint select table . . . . . . . . . . . . . . . . . . . . . . . . . 10-12 table 10-7 breakpoint0 read/write select table . . . . . . . . . . . . . . . . . . . . . 10-13 table 10-8 breakpoint0 condition select table . . . . . . . . . . . . . . . . . . . . . . . 10-13 table 10-9 breakpoint1 read/write select table . . . . . . . . . . . . . . . . . . . . . 10-13 table 10-10 breakpoint1 condition select table . . . . . . . . . . . . . . . . . . . . . . . 10-14 table 10-11 breakpoint0 and breakpoint1 event select table . . . . . . . . . . . . . 10-14 table 10-12 tms sequencing for debug_request. . . . . . . . . . . . . . . . . . . 10-29 table 10-13 tms sequencing for enable_once . . . . . . . . . . . . . . . . . . . . . 10-30 table 10-14 tms sequencing for reading pipeline registers . . . . . . . . . . . . . 10-31 table 11-1 jtag instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-8 table 11-2 DSP56602 boundary scan register (bsr) bit definitions . . . . . . 11-13 table d-1 program word and timing symbols . . . . . . . . . . . . . . . . . . . . . . . . . d-3 table d-2 condition code register (ccr) symbols . . . . . . . . . . . . . . . . . . . . . d-3 table d-3 condition code register notation . . . . . . . . . . . . . . . . . . . . . . . . . . . d-4 table d-4 instruction set summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . d-4
xxii DSP56602 user? manual motorola table d-5 interrupt sources . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . d-14 table d-6 interrupt source priorities within an ipl . . . . . . . . . . . . . . . . . . . . . d-16 table d-7 internal i/o memory map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . d-17 table d-8 list of programmer? sheets . . . . . . . . . . . . . . . . . . . . . . . . . . . . . d-23
motorola DSP56602 user? manual xxiii list of examples example 1-1 sample code listing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-5 example 5-1 move from p source address to p destination address . . . . . . . . . 5-9 example 5-2 bootstrap through external eprom . . . . . . . . . . . . . . . . . . . . . . . . 5-10 example 5-3 pass program memory words to the ogdbr . . . . . . . . . . . . . . . . 5-10 example a-1 sample DSP56602 bootstrap listing . . . . . . . . . . . . . . . . . . . . . . . . a-3 example b-1 DSP56602 x i/o equates . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . b-3 example b-2 DSP56602 interrupt equates. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . b-10 example c-1 DSP56602 bsdl listing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . c-3

motorola DSP56602 user? manual 1-1 section 1 DSP56602 overview
1-2 DSP56602 user? manual motorola DSP56602 overview 1.1 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1-3 1.2 manual conventions . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1-4 1.3 dsp56600 core description . . . . . . . . . . . . . . . . . . . . . . .1-6 1.4 dsp56600 core functional blocks . . . . . . . . . . . . . . . .1-6 1.5 internal buses . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1-11 1.6 DSP56602 architecture overview . . . . . . . . . . . . . . . .1-13
DSP56602 overview introduction motorola DSP56602 user? manual 1-3 1.1 introduction this manual describes the DSP56602 16-bit digital signal processor (dsp), its memory and operating modes, and its peripheral modules. this manual is intended to be used with the dsp56600 family manual (dsp56600fm/ad), which describes the central processing unit (cpu), programming models, and instruction set details. the DSP56602 technical data sheet (DSP56602/d) provides electrical specifications, timing, pinout, and packaging descriptions on the DSP56602. these documents, as well as motorola? dsp development tools, can be obtained through a local motorola semiconductor sales office or authorized distributor. to receive the latest information, access the motorola dsp home page located at the address listed on the back cover of this document. the DSP56602 is a member of the dsp56600 core-based family of programmable cmos dsps. this general purpose dsp combines processing power with configuration flexibility, making it an excellent cost-effective solution for signal processing and control functions. this manual is arranged in the following sections: section 1?sp56602 overview provides a brief overview of the DSP56602, describes the structure of this document, and lists other documentation necessary to use this chip. section 2?ignal/connection description provides a description of the signals present on the pins of the DSP56602, and how these signals are grouped into the various interfaces. section 3?emory maps describes the on-chip memory, structures, registers, and interfaces. section 4?ore configuration describes the registers that must be programmed to properly configure the dsp56600 core when using the DSP56602. section 5?xternal memory interface (port a) describes the external memory interface, which is also referred to as port a. section 6?pio describes the dedicated general purpose input/output (gpio) interface, and the alternate gpio functionality provided on certain on-chip interfaces. section 7?host interface (hi08) describes the 8-bit hi08 host interface. section 8?ynchronous serial interface describes the 16-bit synchronous serial interface (ssi), which communicates with devices such as codecs, other dsps,
1-4 DSP56602 user? manual motorola DSP56602 overview manual conventions microprocessors, and peripherals, to provide the primary data input path. the ssi is a part of port c. section 9?riple timer module describes the three internal timer/counter devices. section 10?n-chip emulation module describes the on-chip emulation (once) module, which is accessed through the joint test action group (jtag) port. section 11?tag port describes the specifics of the jtag port on the DSP56602. appendix a?ootstrap program provides a sample listing of bootstrap code, intended for use as an example of the bootstrap code than can be developed by the customer to start or reset the DSP56602. appendix b? i/o equates lists the input/output equates for the DSP56602. appendix c?sdl listing provides the boundary scan description listing (bsdl) for the DSP56602. appendix d?rogrammer? reference provides programming references and master programming sheets used to program the DSP56602 registers. index provides a cross-reference to topics in this manual. 1.2 manual conventions the following conventions are used in this manual: bits within registers are always listed from most significant bit (msb) to least significant bit (lsb). note: other manuals may use the opposite convention, with bits listed from lsb to msb. bits within a register are indicated aa[n:0] when more than one bit is involved in a description. for purposes of description, the bits are presented as if they are contiguous within a register. however, this is not always the case. refer to the programming model diagrams or to the programmer? sheets to see the exact location of bits within a register. when a bit is described as ?et,?its value is 1. when a bit is described as ?leared,?its value is 0. pins or signals that are asserted low (made active when pulled to ground) have an overbar over their name; for example, the ss0 pin is asserted low.
DSP56602 overview manual conventions motorola DSP56602 user? manual 1-5 hex values are indicated with a dollar sign ($) preceding the hex value as follows: $ffff is the x memory address for the interrupt priority register?ore (ipr-c). code examples are displayed in a monospaced font, as shown in example 1-1 . pins or signals listed in code examples that are asserted low have a tilde in front of their names. in the previous example, line 3 refers to the ss0 pin (shown as ~ss0 ). the word ?ssert?means that a high true (active high) signal is pulled high to v cc or that a low true (active low) signal is pulled low to ground. the word ?eassert?means that a high true signal is pulled low to ground or that a low true signal is pulled high to v cc . see table 1-1 . notes: 1. ground is an acceptable low voltage level. see the appropriate data sheet for the range of acceptable low voltage levels (typically a ttl logic low). 2. v cc is an acceptable high voltage level. see the appropriate data sheet for the range of acceptable high voltage levels (typically a ttl logic high). the word ?eset?is used in four different contexts in this manual: there is a reset pin that is always written as ?eset ? the word ?in?is a generic term for any pin on the chip. there is a reset instruction that is always written as ?eset the word reset refers to the reset function and is written in lower case with a leading capital letter as grammar dictates ?eset?refers to the reset state. example 1-1 sample code listing bfset #$0007,x:pcc; configure: line 1 ; miso0, mosi0, sck0 for spi master line 2 ; ~ss0 as pc3 for gpio line 3 table 1-1 high true / low true signal conventions signal/symbol logic state signal state voltage pin true asserted ground 1 pin false deasserted v cc 2 pin true asserted v cc pin false deasserted ground
1-6 DSP56602 user? manual motorola DSP56602 overview dsp56600 core description 1.3 dsp56600 core description the dsp56600 core is based on the dsp56300 core, with a number of power-saving, performance-enhancing, and cost-reducing features implemented. with its seven-stage instruction pipeline, the dsp56600 core is capable of executing an instruction on every clock cycle. a standard interface between the dsp56600 core and the on-chip memory and peripherals supports many memory and peripheral configurations. complete details of the dsp56600 core are provided in the dsp56600 family manual (dsp56600fm/ad) . the following are some of the features of the dsp56600 core: 60 million instructions per second (mips) with a 60 mhz clock at 2.7 v fully pipelined 16 16-bit parallel multiplier-accumulator (mac) 40-bit parallel barrel shifter highly parallel instruction set with unique dsp addressing modes code compatible with the 56300 core position independent code (pic) support nested hardware do loops fast auto-return interrupts on-chip support for software patching and enhancements on-chip phase lock loop (pll) real-time trace capability via external address bus on-chip emulation (once) module jtag port 1.4 dsp56600 core functional blocks the dsp56600 core provides the following functional blocks: data arithmetic logic unit (data alu) address generation unit (agu) program control unit (pcu) program patch logic
DSP56602 overview dsp56600 core functional blocks motorola DSP56602 user? manual 1-7 pll and clock oscillator expansion memory interface (port a) jtag test access port and on-chip emulation (once) module memory in addition, the DSP56602 provides a set of on-chip peripherals, described in DSP56602 architecture overview on page 1-13. 1.4.1 data arithmetic logic unit (alu) the data arithmetic logic unit (alu) performs all the arithmetic and logical operations on data operands in the dsp56600 core. the components of the data alu are as follows: four 16-bit input general purpose registers: x1, x0, y1, and y0 a parallel, fully pipelined multiplier-accumulator unit (mac) six data alu registers (a2, a1, a0, b2, b1, and b0) that are concatenated into two general purpose, 40-bit accumulators, a and b an accumulator shifter that is an asynchronous parallel shifter with a 40-bit input and a 40-bit output a bit field unit (bfu) with a 40-bit barrel shifter two data bus shifter/limiter circuits 1.4.1.1 data alu registers the data alu registers can be read or written over the x data bus (xdb) and the y data bus (ydb) as 16- or 32-bit operands. the source operands for the data alu, which can be 16, 32, or 40 bits, always originate from data alu registers. the results of all data alu operations are stored in an accumulator. all the data alu operations are performed in 2 clock cycles in pipeline fashion so that a new instruction can be initiated in every clock, yielding an effective execution rate of one instruction per clock cycle. the destination of every arithmetic operation can be used as a source operand for the immediate following operation without penalty. 1.4.1.2 multiplier-accumulator (mac) the multiplier-accumulator (mac) unit comprises the main arithmetic processing unit of the dsp56600 core and performs all of the calculations on data operands. in the case of arithmetic instructions, the unit accepts as many as three input operands and outputs
1-8 DSP56602 user? manual motorola DSP56602 overview dsp56600 core functional blocks one 40-bit result of the following form, extension:most significant product:least significant product (ext:msp:lsp). the multiplier executes 16-bit 16-bit, parallel, fractional multiplies, between two?-complement signed, unsigned, or mixed operands. the 32-bit product is right-justified and added to the 40-bit contents of either the a or b accumulator. a 40-bit result can be stored as a 16-bit operand. the lsp can either be truncated or rounded into the msp. rounding is performed if specified. 1.4.2 address generation unit the agu performs the effective address calculations using integer arithmetic necessary to address data operands in memory and contains the registers used to generate the addresses. it implements four types of arithmetic: linear, modulo, multiple wrap-around modulo, and reverse-carry. the agu operates in parallel with other chip resources to minimize address-generation overhead. the agu is divided into two halves, each with its own address arithmetic logic unit (address alu). each address alu has four sets of register triplets, and each register triplet is composed of an address register, an offset register, and a modifier register. the two address alus are identical. each contains a 16-bit full adder (called an offset adder). a second full adder (called a modulo adder) adds the summed result of the first full adder to a modulo value that is stored in its respective modifier register. a third full adder (called a reverse-carry adder) is also provided. the offset adder and the reverse-carry adder are in parallel and share common inputs. the only difference between them is that the carry propagates in opposite directions. test logic determines which of the three summed results of the full adders is output. each address alu can update one address register from its respective address register file during 1 instruction cycle. the contents of the associated modifier register specifies the type of arithmetic to be used in the address register update calculation. the modifier value is decoded in the address alu. 1.4.3 program control unit the program control unit (pcu) performs instruction prefetch, instruction decoding, hardware do loop control, and exception processing. the pcu implements a
DSP56602 overview dsp56600 core functional blocks motorola DSP56602 user? manual 1-9 seven-stage pipeline and controls the different processing states of the dsp56600 core. the pcu consists of three hardware blocks: program decode controller (pdc) program address generator (pag) program interrupt controller (pic) the pdc decodes the 24-bit instruction loaded into the instruction latch and generates all signals necessary for pipeline control. the pag contains all the hardware needed for program address generation, system stack, and loop control. the pic arbitrates among all interrupt requests (internal interrupts, as well as the five external requests irqa , irqb , irqc , irqd , and nmi ), and generates the appropriate interrupt vector address. the pcu implements its functions using the following registers: pc?rogram counter register sr?tatus register la?oop address register lc?oop counter register vba?ector base address register sz?ize register sp?tack pointer omr?perating mode register sc?tack counter register the pcu also includes a hardware system stack (ss). 1.4.4 program patch logic the program patch logic (ppl) block provides the dsp56600 core user a way to fix the program code in the on-chip rom without generating a new mask. implementing the code correction is done by replacing a piece of rom-based code with a patch program stored in ram. the ppl consists of four patch address registers (par1?ar4) and four patch address comparators. each par points to a starting location in the rom code where the program flow is to be changed. the pc register in the pcu is compared to each par. when an address of a fetched instruction is identical to an address stored in one of the pars, the program data bus (pdb) is forced to a corresponding jmp
1-10 DSP56602 user? manual motorola DSP56602 overview dsp56600 core functional blocks instruction, replacing the instruction that otherwise would have been fetched from the rom. 1.4.5 pll and clock oscillator the dsp56600 core features a phase lock loop (pll) clock oscillator in its central processing module. the pll allows the processor to operate at a high internal clock frequency using a low frequency clock input, a feature that offers two immediate benefits: a lower frequency clock input reduces the overall electromagnetic interference generated by a system. the ability to oscillate at different frequencies reduces costs by eliminating the need to add additional oscillators to a system. the clock generator in the dsp56600 core is composed of two main blocks: the pll, which performs clock input division, frequency multiplication, and skew elimination; and the clock generator (clkgen), which performs low power division and clock pulse generation. 1.4.6 expansion memory interface (port a) port a is the memory expansion port used for both program and data memory. it provides an easy to use, low part-count connection with fast or slow static memories and with i/o devices. the port a data bus is 24 bits wide with a separate 16-bit address bus capable of a sustained rate of one memory access per two clock cycles. external memory can be as large as 64 k 24-bit program memory space, depending on chip configuration. an internal wait state generator can be programmed to insert as many as thirty-one wait states if access to slower memory or i/o device is required. for power-sensitive applications and applications that do not require external memory, port a can be fully disabled. 1.4.7 jtag test access port and on-chip emulation module the dsp56600 core provides a dedicated user-accessible test access port (tap) that is fully compatible with the ieee 1149.1 standard test access port and boundary scan architecture . problems associated with testing high density circuit boards have led to development of this standard under the sponsorship of the test technology committee
DSP56602 overview internal buses motorola DSP56602 user? manual 1-11 of ieee and the joint test action group (jtag). the dsp56600 core implementation supports circuit-board test strategies based on this standard. the test logic includes a tap consisting of four dedicated signal pins, a 16-state controller, and three test data registers. a boundary scan register links all device signal pins into a single shift register. the test logic, implemented utilizing static logic design, is independent of the device system logic. more information on the jtag port is provided in section 11, jtag port. the on-chip emulation (once) module provides a means of interacting with the dsp56600 core and its peripherals non-intrusively so that a user can examine registers, memory, or on-chip peripherals. this facilitates hardware and software development on the dsp56600 core processor. once module functions are provided through the jtag tap pins. more information on the once module is provided in section 10, on-chip emulation module. 1.4.8 on-chip memory the memory space of the dsp56600 core is partitioned into program memory space, x data memory space, and y data memory space. the data memory space is divided into x data memory and to y data memory in order to work with the two address alus and to feed two operands simultaneously to the data alu. memory space includes internal ram and rom and can be expanded off-chip under software control. more information on the internal memory is provided in section 3, memory maps. 1.5 internal buses to provide data exchange between these blocks, the following buses are implemented: peripheral i/o expansion bus (pio_eb) to peripherals program memory expansion bus (pm_eb) to program rom x memory expansion bus (xm_eb) to x memory y memory expansion bus (ym_eb) to y memory global data bus (gdb) between program control unit and other core structures program data bus (pdb) for carrying program data throughout the core x memory data bus (xdb) for carrying x data throughout the core
1-12 DSP56602 user? manual motorola DSP56602 overview internal buses y memory data bus (ydb) for carrying y data throughout the core program address bus (pab) for carrying program memory addresses throughout the core x memory address bus (xab) for carrying x memory addresses throughout the core y memory address bus (yab) for carrying y memory addresses throughout the core with the exception of the program data bus (pdb), all internal buses on the dsp56600 family members are 16-bit buses. the pdb is a 24-bit bus. figure 1-1 provides a block diagram of the DSP56602. figure 1-1 DSP56602 block diagram extal program memory rom 34 k 24 ram 0.5 k 24 yab xab pab ydb xdb pdb gdb modc/irqc modd/irqd address 4 data control 6 16 24 16 memory peripheral ym_eb xm_eb pm_eb expansion area 6 jtag 5 reset modb/irqb pcap 3 once clkout x data memory rom 6 k 16 ram 4.25 k 16 dsp56600 16-bit core pio_eb area expansion moda/irqa pinit/nmi de power manage- ment data alu 16 16 + 40 ? 40-bit mac two 40-bit accumulators 40-bit barrel shifter external bus interface program interrupt controller program decode controller program address generator program patch detector address generation unit internal data bus switch clock generator pll triple timer or gpio pins dedicated gpio pins host interface hi08 or gpio pins ssi interface or gpio pins y data memory rom 8 k 16 ram 4.25 k 16 aa1096
DSP56602 overview DSP56602 architecture overview motorola DSP56602 user? manual 1-13 1.6 DSP56602 architecture overview the DSP56602 is designed to perform a wide variety of fixed-point digital signal processing functions. in addition to the core features previously discussed, the DSP56602 provides the following peripherals: three dedicated general purpose i/o (gpio) pins as many as thirty-one additional user-configurable gpio pins 8-bit parallel host interface (hi08) to external hosts dual synchronous serial interface (ssi) triple timer module four external interrupt/mode control lines 1.6.1 gpio functionality the general purpose i/o (gpio) port consists of three bidirectional pins, each pin separately controlled. functionality is controlled by three memory-mapped registers. gpio functionality is also available on the hi08, ssi, and timer pins when these pins are not otherwise being used by their peripherals. the techniques for register programming for all gpio functionality is very similar between these interfaces. a maximum of thirty-four gpio pins can be configured. 1.6.2 host interface (hi08) the host interface (hi08) is a byte-wide, full-duplex, double-buffered, parallel port that can be connected directly to the data bus of a host processor. the hi08 supports a variety of buses, and provides connection with a number of industry-standard dsps, microcomputers, and microprocessors without requiring any additional logic. the dsp core views the hi08 as a memory-mapped peripheral occupying eight 16-bit words in data memory space. the dsp can use the hi08 as a memory-mapped peripheral, using either standard polled or interrupt programming techniques. separate transmit and receive data registers are double-buffered to allow the dsp and host processor to efficiently transfer data at high speed. memory mapping allows dsp core communication with the hi08 registers to be accomplished using standard instructions and addressing modes.
1-14 DSP56602 user? manual motorola DSP56602 overview DSP56602 architecture overview 1.6.3 synchronous serial interface (ssi) the DSP56602 provides two independent and identical synchronous serial interfaces (ssis). each ssi provides a full-duplex serial port for communication with a variety of serial devices, including one or more industry-standard codecs, other dsps, microprocessors, and peripherals that implement the motorola spi. the ssi consists of independent transmitter and receiver sections and a common ssi clock generator. the capabilities of the ssi include: independent (asynchronous) or shared (synchronous) transmit and receive sections with separate or shared internal/external clocks and frame syncs normal mode operation using frame sync network mode operation with as many as 32 time slots programmable word length (8, 12, or 16 bits) program options for frame synchronization and clock generation 1.6.4 triple timer the triple timer module is composed of a common 14-bit prescaler and three independent and identical general purpose 16-bit timer/event counters, each one having its own memory-mapped register set. each timer can use internal or external clocking and can interrupt the dsp after a specified number of events (clocks) or can signal an external device after counting internal events. each timer connects to the external world through one bidirectional pin. when this pin is configured as an input, the timer can function as an external event counter or measures external pulse width/signal period. when the pin is used as an output, the timer can function as either a timer, a watchdog, or a pulse width modulator (pwm).
motorola DSP56602 user? manual 2-1 section 2 signal/connection description
2-2 DSP56602 user? manual motorola signal/connection description 2.1 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2-3 2.2 power . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2-5 2.3 ground. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2-6 2.4 clock and phase lock loop. . . . . . . . . . . . . . . . . . . . . . .2-7 2.5 interrupt and mode control . . . . . . . . . . . . . . . . . . . . .2-8 2.6 external memory interface (port a) . . . . . . . . . . . .2-10 2.7 host interface (hi08) . . . . . . . . . . . . . . . . . . . . . . . . . . . .2-12 2.8 synchronous serial interface 0 (ssi0) . . . . . . . . . . .2-18 2.9 synchronous serial interface 1 (ssi1) . . . . . . . . . . .2-21 2.10 general purpose i/o (gpio). . . . . . . . . . . . . . . . . . . . . . .2-24 2.11 triple timer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2-25 2.12 jtag/once interface. . . . . . . . . . . . . . . . . . . . . . . . . . . . .2-26
signal/connection description introduction motorola DSP56602 user? manual 2-3 2.1 introduction the input and output signals of the DSP56602 are organized into functional groups, as shown in table 2-1 and as illustrated in figure 2-1 . in table 2-2 through table 2-13 , each table row describes the signal or signals present on a pin. the DSP56602 operates from a 3 v supply; however, some of the inputs can tolerate 5 v. a special notice for this feature is added to the signal descriptions of those inputs. table 2-1 functional group signal allocations functional group number of signals detailed description power (v cc ) 19 table 2-2 ground (gnd) 19 table 2-3 pll and clock signals 5 table 2-4 interrupt and mode control 5 table 2-5 external memory interface (also referred to as port a) address bus 16 table 2-6 data bus 24 bus control 4 host interface (hi08) port b (gpio) 16 table 2-8 synchronous serial interface 0 (ssi0) port c (gpio) 6 table 2-9 synchronous serial interface 1 (ssi1) port d (gpio) 6 table 2-10 general purpose input/output (gpio) 3 table 2-11 triple timer 3 table 2-12 jtag interface/on-chip emulation (once) module 6 table 2-13
2-4 DSP56602 user? manual motorola signal/connection description introduction figure 2-1 DSP56602 signals identified by functional group DSP56602 24 16 external address bus external data bus external bus control synchronous serial interface port 0 (ssi0) 2 timers 3 clock/pll jtag/once port power inputs: address bus bus control data bus hi08 pll internal logic high-voltage internal logic low-voltage ssi/gpio/timer a0?15 d0?23 rd wr at mcs tck tdi tdo tms trst de clkout pcap pinit/nmi v cca v ccc v ccd v cch v ccp v ccqh v ccql v ccs 3 dedicated general purpose input/output port (gpio) 2 4 4 3 grounds: address bus bus control data bus hi08 pll pll internal logic ssi/gpio/timer gnd a gnd c gnd d gnd h gnd p gnd p1 gnd q gnd s 4 4 4 2 interrupt/ mode control moda/irqa modb/irqb modc/irqc modd/irqd reset host interface (hi08) port 1 gpio0 gpio1 gpio2 8 3 2 extal xtal synchronous serial interface port 1 (ssi1) 2 3 port a 2 note: 1. the hi08 port supports a non-multiplexed or a multiplexed bus, single or double data strobe (ds), and single or double host request (hr) configurations. since each these modes is configured independently, any combination of these modes is possible. the hi08 signals can also be configured alternately as gpio signals (pb0?b15). 2. the ssi0 and ssi1 signals can be configured alternatively as port c gpio signals (pc0?c5) and port d gpio signals (pd0?d5), respectively. 3. tio0?io2 can be configured alternatively as gpio signals. non-multiplexed bus hd0?d7 ha0 ha1 ha2 hcs/ hcs single ds hrw hds /hds single hr hreq /hreq hack /hack multiplexed bus had0?ad7 has /has ha8 ha9 ha10 double ds hrd/hrd hwr /hwr double hr htrq /htrq hrrq /hrrq port b gpio pb0?b7 pb8 pb9 pb10 pb13 pb11 pb12 pb14 pb15 sc00?c02 sck0 srd0 std0 port c gpio pc0?c2 pc3 pc4 pc5 sc10?c12 sck1 srd1 std1 port d gpio pd0?d2 pd3 pd4 pd5 tio0 tio1 tio2 timer gpio tio0 tio1 tio2 aa1097
signal/connection description power motorola DSP56602 user? manual 2-5 2.2 power table 2-2 power inputs signal name (no. of pins) signal description v cca (3) address bus power ? cca is an isolated power for sections of address bus i/o drivers, and must be tied externally to all other chip power inputs, except for the v ccql input. the user must provide adequate external decoupling capacitors. v ccc (1) bus control power ? ccc is an isolated power for the bus control i/o drivers, and must be tied to all other chip power inputs externally, except for the v ccql input. the user must provide adequate external decoupling capacitors. v ccd (4) data bus power ? ccd is an isolated power for sections of data bus i/o drivers, and must be tied to all other chip power inputs externally, except for the v ccql input. the user must provide adequate external decoupling capacitors. v cch (1) host power ? cch is an isolated power for the hi08 logic, and must be tied to all other chip power inputs externally, except for the v ccql input. the user must provide adequate external decoupling capacitors. v ccp (1) pll power ? ccp is v cc dedicated for phase lock loop (pll) use. the voltage should be well-regulated and the input should be provided with an extremely low impedance path to the v cc power rail. v ccqh (3) quiet power high voltage ? ccqh is an isolated power for the cpu logic, and must be tied to all other chip power inputs externally, except for the v ccql input. the user must provide adequate external decoupling capacitors. the voltage supplied to these inputs should equal the voltage supplied to i/o power inputs v cca , v ccc , v ccd , v cch , and v ccs . v ccql (4) quiet power low voltage ? ccql is an isolated power for the cpu logic, and should not be tied to the other chip power inputs. the user must provide adequate external decoupling capacitors. v ccs (2) ssi, gpio, and timers power ? ccs is an isolated power for the ssis, gpio, and timers logic, and must be tied to all other chip power inputs externally, except for the v ccql inputs. the user must provide adequate external decoupling capacitors.
2-6 DSP56602 user? manual motorola signal/connection description ground 2.3 ground table 2-3 grounds signal name (no. of pins) signal description gnd a (4) address bus ground ?nd a is an isolated ground for sections of address bus i/o drivers, and must be tied externally to all other chip ground connections. the user must provide adequate external decoupling capacitors. gnd c (2) bus control ground ?nd c is an isolated ground for the bus control i/o drivers, and must be tied externally to all other chip ground connections. the user must provide adequate external decoupling capacitors. gnd d (4) data bus ground ?nd d is an isolated ground for sections of the data bus i/o drivers, and must be tied externally to all other chip ground connections. the user must provide adequate external decoupling capacitors. gnd h (1) host ground ?nd h is an isolated ground for the hi08 i/o drivers, and must be tied externally to all other chip ground connections. the user must provide adequate external decoupling capacitors. gnd p (1) pll ground ?nd p is ground dedicated for pll use, and should be provided with an extremely low impedance path to ground. v ccp should be bypassed to gnd p with a 0.1 ? capacitor located as close as possible to the chip package. gnd p1 (1) pll ground 1 ?nd p1 is ground dedicated for pll use, and should be provided with an extremely low impedance path to ground. gnd q (4) quiet ground ?nd q is an isolated ground for the cpu logic, and must be tied externally to all other chip ground connections. the user must provide adequate external decoupling capacitors. gnd s (2) ssis, gpio, and timers ground ?nds is an isolated ground for the ssis, gpio, and timers logic, and must be tied externally to all other chip ground connections. the user must provide adequate external decoupling capacitors.
signal/connection description clock and phase lock loop motorola DSP56602 user? manual 2-7 2.4 clock and phase lock loop table 2-4 clock and pll signals signal name signal type state during reset signal description extal input input external clock/crystal input ?xtal interfaces the internal crystal oscillator input to an external crystal or an external clock. xtal output chip- driven crystal output ?tal connects the internal crystal oscillator output to an external crystal. if an external clock is used, leave xtal unconnected. pcap input indeter- minate pll capacitor ?cap is an input connecting an off-chip capacitor to the pll filter. connect one capacitor terminal to pcap and the other terminal to v ccp . if the pll is not used, pcap may be tied to v cc , gnd, or left floating. clkout output chip- driven clock output ?lkout provides an output clock synchronized to the internal core clock phase. when the pll is enabled, the division factor (df) equals one, and the multiplication factor (mf) is less than or equal to four, clkout is also synchronized to extal when the pll is disabled, the clkout frequency is half the frequency of extal. pinit nmi input input input pll initialize ?uring assertion of reset , the value of pinit is written into the pll enable (pen) bit of the pll control register 1 (pctl1), determining whether the pll is enabled or disabled. when this input is high during reset assertion, the pll is enabled following reset deassertion. non-maskable interrupt ?fter reset deassertion and during normal instruction processing, the nmi schmitt-trigger input is a negative-edge-triggered non-maskable interrupt (nmi) request internally synchronized to clkout. this input can tolerate 5 v.
2-8 DSP56602 user? manual motorola signal/connection description interrupt and mode control 2.5 interrupt and mode control table 2-5 interrupt and mode control signals signal name signal type state during reset signal description reset input input reset ?eset is an active low, schmitt-trigger input. deassertion of the reset signal is internally synchronized to the clock out (clkout). when asserted, the chip is placed in the reset state and the internal phase generator is reset. the schmitt-trigger input allows a slowly rising input, such as a capacitor charging, to reliably reset the chip. if the reset signal is deasserted synchronous to clkout, exact start-up timing is guaranteed, allowing multiple processors to start up synchronously and operate together. when the reset signal is deasserted, the initial chip operating mode is latched from the moda, modb, modc, and modd inputs. this input can tolerate 5 v. moda irqa input input input mode select a ?oda selects the initial chip operating mode during hardware reset. moda, modb, modc, and modd select one of sixteen initial chip operating modes latched into the operating mode register (omr) when the reset signal is deasserted. external interrupt request a ?ollowing reset deassertion, moda becomes irqa , a level-sensitive or negative-edge- triggered, maskable interrupt request input during normal instruction processing. if irqa is asserted synchronous to clkout, multiple processors can be resynchronized using the wait instruction and asserting irqa to exit the wait state. if the processor is in the stop standby state and irqa is asserted, the processor exits the stop state. this is an active low schmitt-trigger input, internally synchronized to clkout. this input can tolerate 5 v.
signal/connection description interrupt and mode control motorola DSP56602 user? manual 2-9 modb irqb input input input mode select b ?odb selects the initial chip operating mode during hardware reset. moda, modb, modc, and modd select one of sixteen initial chip operating modes latched into the omr when the reset signal is deasserted. external interrupt request b ?ollowing reset deassertion, modb becomes irqb , a level-sensitive or negative-edge- triggered, maskable interrupt request input during normal instruction processing. if irqb is asserted synchronous to clkout, multiple processors can be resynchronized using the wait instruction and asserting irqb to exit the wait state. this is an active low schmitt-trigger input, internally synchronized to clkout. this input can tolerate 5 v. modc irqc input input input mode select c?odc selects the initial chip operating mode during hardware reset. moda, modb, modc, and modd select one of sixteen initial chip operating modes latched into the omr when the reset signal is deasserted. external interrupt request c?ollowing reset deassertion, modc becomes irqc , a level-sensitive or negative-edge- triggered, maskable interrupt request input during normal instruction processing. if irqc is asserted synchronous to clkout, multiple processors can be resynchronized using the wait instruction and asserting irqc to exit the wait state. this is an active low schmitt-trigger input, internally synchronized to clkout. this input can tolerate 5 v. table 2-5 interrupt and mode control signals (continued) signal name signal type state during reset signal description
2-10 DSP56602 user? manual motorola signal/connection description external memory interface (port a) 2.6 external memory interface (port a) modd irqd input input input mode select d ?odd selects the initial chip operating mode during hardware reset. moda, modb, modc, and modd select one of sixteen initial chip operating modes latched into the omr when the reset signal is deasserted. external interrupt request c?ollowing reset deassertion, modd becomes irqd , a level-sensitive or negative-edge- triggered, maskable interrupt request input during normal instruction processing. if irqd is asserted synchronous to clkout, multiple processors can be resynchronized using the wait instruction and asserting irqd to exit the wait state. this is an active low schmitt-trigger input, internally synchronized to clkout. this input can tolerate 5 v. note: see also pinit/nmi in table 2-4 clock and pll signals on page 2-7. table 2-6 external memory interface (port a) signals signal name signal type state during reset signal description a0?15 output set according to chip operating mode* address bus ?hese active high outputs specify the address for external program memory accesses. to minimize power dissipation, a0?15 do not change state when external memory spaces are not being accessed. d0?23 input/ output tri-stated data bus ?hese active high, bidirectional input/outputs provide the bidirectional data bus for external program memory accesses. d0?23 are tri-stated when no external bus activity occurs, and during hardware reset. mcs output pulled high internally memory chip select ?his signal is an active low output, and is asserted when an external memory access occurs. mcs is deasserted during hardware reset. table 2-5 interrupt and mode control signals (continued) signal name signal type state during reset signal description
signal/connection description external memory interface (port a) motorola DSP56602 user? manual 2-11 rd output pulled high internally read enable ?his signal is an active low output. rd is asserted to read external memory on the data bus (d0?23). rd is deasserted during hardware reset. wr output pulled high internally write enable ?his signal is an active low output. wr is asserted to write external memory on the data bus (d0?23). wr is deasserted during hardware reset. at output pulled high internally address tracing ?his signal is an active low output. at is asserted (for half of a clock cycle) whenever a new address is driven on the address bus (a0?15) in the program address tracing mode. the new address is either a reflection of internal fetch or internal program space move instruction or an external address driven for an external access. at is deasserted during hardware reset. note: * the a0?15 pins are asserted according to the selected chip operating mode, as determined by the values on the moda?odd pins. each mode has a different reset address. a0?15 are latched to the value of that reset address minus 1. for example, if the reset address for a selected operating mode is $0800, the address bus is asserted to $07ff. table 2-6 external memory interface (port a) signals (continued) signal name signal type state during reset signal description
2-12 DSP56602 user? manual motorola signal/connection description host interface (hi08) 2.7 host interface (hi08) the hi08 provides a fast 8-bit port that can be connected directly to the host bus. the hi08 supports a variety of standard buses, and can be directly connected to a number of industry-standard microcomputers, microprocessors, and dsps. 2.7.1 host port usage considerations careful synchronization is required when reading multiple-bit registers that are written by another asynchronous system. this is a common problem when two asynchronous systems are connected (as they are in the host port). the considerations for proper operation are discussed in the following table: 2.7.2 host port configuration the signal functions associated with the hi08 vary according to the configuration determined by the hi08 port control register (hpcr). refer to section 7, host interface (hi08), for detailed descriptions of this and the other configuration registers used with the hi08. table 2-7 host port usage considerations action description asynchronous read of receive byte registers when reading the receive byte registers, receive high (rxh) register or receive low (rxl) register, the host interface programmer should use interrupts or poll the receive register data full (rxdf) flag, which indicates that data is available. this assures that the data in the receive byte registers is valid. asynchronous write to transmit byte registers the host interface programmer should not write to the transmit byte registers, transmit high (txh) register or transmit low (txl) register, unless the transmit register data empty (txde) bit is set, which indicates that the transmit byte registers are empty. this guarantees that the transmit byte registers transfer valid data to the host receive (hrx) register. asynchronous write to host vector the host interface programmer should change the host vector (hv) register only when the host command (hc) bit is clear. this guarantees that the dsp interrupt control logic receives a stable vector.
signal/connection description host interface (hi08) motorola DSP56602 user? manual 2-13 table 2-8 host interface signals signal name signal type state during reset signal description hd0?d7 had0 had7 pb0?b7 bi- directional bi- directional input or output discon- nected internally host data bus ?hen the hi08 is programmed to interface a non-multiplexed host bus and the hi function is selected, these signals are lines 0? of the host data bidirectional tri-state bus (hd0?d7). host address and data bus ?hen the hi08 is programmed to interface a multiplexed host bus and the hi function is selected, these signals are lines 0? of the host address/data multiplexed bidirectional tri-state bus (had0?ad7). port b 0? ?hen the hi08 is configured as gpio through the hi08 port control register (hpcr), these signals are individually programmed as inputs or outputs through the hi08 data direction register (hddr). when configured as an input, these pins can tolerate 5 v. these pins are electrically disconnected internally during stop mode. ha0 has /has pb8 input input input or output discon- nected internally host address input 0 ?hen the hi08 is programmed to interface a non-multiplexed host bus and the hi function is selected, this signal is line 0 of the host address input bus (ha0). host address strobe ?hen the hi08 is programmed to interface a multiplexed host bus and the hi function is selected, this signal is the host address strobe (has ) schmitt-trigger input. the polarity of the address strobe is programmable. port b 8 ?hen the hi08 is configured as gpio through the hpcr, this signal is individually programmed as an input or output through the hddr. when configured as an input, this pin can tolerate 5 v. this pin is electrically disconnected internally during stop mode.
2-14 DSP56602 user? manual motorola signal/connection description host interface (hi08) ha1 ha8 pb9 input input input or output discon- nected internally host address input 1 ?hen the hi08 is programmed to interface a non-multiplexed host bus and the hi function is selected, this signal is line one of the host address input bus (ha1). host address 8 ?hen the hi08 is programmed to interface a multiplexed host bus and the hi function is selected, this signal is line eight of the input host address bus (ha8). port b 9 ?hen the hi08 is configured as gpio through the hpcr, this signal is individually programmed as an input or output through the hddr. when configured as an input, this pin can tolerate 5 v. this pin is electrically disconnected internally during stop mode. ha2 ha9 pb10 input input input or output discon- nected internally host address input 2 ?hen the hi08 is programmed to interface a non-multiplexed host bus and the hi function is selected, this signal is line two of the host address input bus (ha2). host address 9 ?hen the hi08 is programmed to interface a multiplexed host bus and the hi function is selected, this signal is line nine of the input host address bus (ha9). port b 10 ?hen the hi08 is configured as gpio through the hpcr, this signal is individually programmed as an input or output through the hddr. when configured as an input, this pin can tolerate 5 v. this pin is electrically disconnected internally during stop mode. table 2-8 host interface signals (continued) signal name signal type state during reset signal description
signal/connection description host interface (hi08) motorola DSP56602 user? manual 2-15 hrw hrd / hrd pb11 input input input or output discon- nected internally host read/write ?hen the hi08 is programmed to interface a single-data-strobe host bus and the hi function is selected, this signal is the read/write input (hrw). host read data ?hen the hi08 is programmed to interface a double-data-strobe host bus and the hi function is selected, this signal is the read data strobe schmitt-trigger input (hrd ). the polarity of the data strobe is programmable. port b 11 ?hen the hi08 is configured as gpio through the hpcr, this signal is individually programmed as an input or output through the hddr. when configured as an input, this pin can tolerate 5 v. this pin is electrically disconnected internally during stop mode. h ds /hds hwr / hwr pb12 input input input or output discon- nected internally host data strobe ?hen the hi08 is programmed to interface a single-data-strobe host bus and the hi function is selected, this signal is the host data strobe schmitt-trigger input (hds ). the polarity of the data strobe is programmable. host write enable ?hen the hi08 is programmed to interface a double-data-strobe host bus and the hi function is selected, this signal is the write data strobe schmitt-trigger input (hwr ). the polarity of the data strobe is programmable. port b 12 ?hen the hi08 is configured as gpio through the hpcr, this signal is individually programmed as an input or output through the hddr. when configured as an input, this pin can tolerate 5 v. this pin is electrically disconnected internally during stop mode. table 2-8 host interface signals (continued) signal name signal type state during reset signal description
2-16 DSP56602 user? manual motorola signal/connection description host interface (hi08) h c s /hcs ha10 pb13 input input input or output discon- nected internally host chip select ?hen the hi08 is programmed to interface a non-multiplexed host bus and the hi function is selected, this signal is the host chip select input (hcs ). the polarity of the chip select is programmable. host address 10 ?hen the hi08 is programmed to interface a multiplexed host bus and the hi function is selected, this signal is line 10 of the input host address bus (ha10). port b 13 ?hen the hi08 is configured as gpio through the hpcr, this signal is individually programmed as an input or output through the hddr. when configured as an input, this pin can tolerate 5 v. this pin is electrically disconnected internally during stop mode. hr eq / hreq htrq / htrq pb14 output output input or output discon- nected internally host request ?hen the hi08 is programmed to interface a single host request host bus and the hi function is selected, this signal is the host request output (hreq ). the polarity of the host request is programmable. the host request can be programmed as a driven or open-drain output. transmit host request ?hen the hi08 is programmed to interface a double host request host bus and the hi function is selected, this signal is the transmit host request output (htrq ). the polarity of the host request is programmable. the host request can be programmed as a driven or open-drain output. port b 14 ?hen the hi08 is programmed to interface a multiplexed host bus and the signal is configured as gpio through the hpcr, this signal is individually programmed as an input or output through the hddr. when configured as an input, this pin can tolerate 5 v. this pin is electrically disconnected internally during stop mode. table 2-8 host interface signals (continued) signal name signal type state during reset signal description
signal/connection description host interface (hi08) motorola DSP56602 user? manual 2-17 ha ck / hack hrrq / hrrq pb15 input output input or output discon- nected internally host acknowledge ?hen the hi08 is programmed to interface a single host request host bus and the hi function is selected, this signal is the host acknowledge schmitt-trigger input (hack ). the polarity of the host acknowledge is programmable. receive host request ?hen the hi08 is programmed to interface a double host request host bus and the hi function is selected, this signal is the receive host request output (hrrq ). the polarity of the host request is programmable. the host request can be programmed as a driven or open-drain output. port b 15 ?hen the hi08 is configured as gpio through the hpcr, this signal is individually programmed as an input or output through the hddr. when configured as an input, this pin can tolerate 5 v. this pin is electrically disconnected internally during stop mode. table 2-8 host interface signals (continued) signal name signal type state during reset signal description
2-18 DSP56602 user? manual motorola signal/connection description synchronous serial interface 0 (ssi0) 2.8 synchronous serial interface 0 (ssi0) two identical synchronous serial interfaces (ssi0 and ssi1) provide a full-duplex serial port for serial communication with a variety of serial devices including one or more industry-standard codecs, other dsps, or microprocessors. when either ssi port is disabled, it can be used for general purpose i/o (gpio). table 2-9 synchronous serial interface 0 (ssi0) signal name signal type state during reset signal description sc00 pc0 input or output input or output input serial control signal 0 ?he function of sc00 is determined by the selection of either synchronous or asynchronous mode. for asynchronous mode, this signal is used for the receive clock i/o (schmitt-trigger input). for synchronous mode, this signal is used for or for serial i/o flag 0. port c 0 ?hen configured as pc0, signal direction is controlled through the ssi0 port direction control register (prrc). the signal can be configured as ssi signal sc00 through the ssi0 port control register (pcrc). when configured as an input, this pin can tolerate 5 v. this pin is electrically disconnected internally during stop mode. sc01 pc1 input or output input or output input serial control signal 1 ?he function of sc00 is determined by the selection of either synchronous or asynchronous mode. for asynchronous mode, this signal is used for the receive clock i/o (schmitt-trigger input). for synchronous mode, this signal is used for serial i/o flag 1. port c 1 ?hen configured as pc1, signal direction is controlled through the prrc register. the signal can be configured as an ssi signal sc01 through the pcrc register. when configured as an input, this pin can tolerate 5 v. this pin is electrically disconnected internally during stop mode.
signal/connection description synchronous serial interface 0 (ssi0) motorola DSP56602 user? manual 2-19 sc02 pc2 input or output input or output input serial control signal 2 ?c02 is the frame sync for both the transmitter and receiver in synchronous mode, and for the transmitter only in asynchronous mode. when configured as an output, this signal is the internally generated frame sync signal. when configured as an input, this signal receives an external frame sync signal for the transmitter (and the receiver in synchronous operation). port c 2 ?hen configured as pc2, signal direction is controlled through the prrc register. the signal can be configured as an ssi signal sc02 through the pcrc register. when configured as an input, this pin can tolerate 5 v. this pin is electrically disconnected internally during stop mode. sck0 pc3 input or output input or output input serial clock ?ck0 is a bidirectional schmitt-trigger input signal providing the serial bit rate clock for the ssi. the sck0 is a clock input or output used by both the transmitter and receiver in synchronous modes, or by the transmitter in asynchronous modes. although an external serial clock can be independent of and asynchronous to the dsp system clock, it must exceed the minimum clock cycle time of 6t (i.e., the system clock frequency must be at least three times the external ssi clock frequency). the ssi needs at least three dsp phases inside each half of the serial clock. port c 3 ?hen configured as pc3, signal direction is controlled through the prrc register. the signal can be configured as an ssi signal sck0 through the pcrc register. when configured as an input, this pin can tolerate 5 v. this pin is electrically disconnected internally during stop mode. table 2-9 synchronous serial interface 0 (ssi0) (continued) signal name signal type state during reset signal description
2-20 DSP56602 user? manual motorola signal/connection description synchronous serial interface 0 (ssi0) srd0 pc4 input input or output input serial receive data ?rd0 receives serial data and transfers the data to the ssi receive shift register. srd0 is an input when data is being received. port c 4 ?hen configured as pc4, signal directions is controlled through the prrc register. the signal can be configured as an ssi signal srd0 through the pcrc register. when configured as an input, this pin can tolerate 5 v. this pin is electrically disconnected internally during stop mode. std0 pc5 output input or output input serial transmit data ?td0 is used for transmitting data from the serial transmit shift register. std0 is an output when data is being transmitted. port c 5 ?hen configured as pc5, signal directions is controlled through the prrc register. the signal can be configured as an ssi signal std0 through the pcrc register. when configured as an input, this pin can tolerate 5 v. this pin is electrically disconnected internally during stop mode. table 2-9 synchronous serial interface 0 (ssi0) (continued) signal name signal type state during reset signal description
signal/connection description synchronous serial interface 1 (ssi1) motorola DSP56602 user? manual 2-21 2.9 synchronous serial interface 1 (ssi1) table 2-10 synchronous serial interface 1 (ssi1) signal name signal type state during reset signal description sc10 pd0 input or output input or output input serial control signal 0 ?he function of sc10 is determined by the selection of either synchronous or asynchronous mode. for asynchronous mode, this signal is used for the receive clock i/o (schmitt-trigger input). for synchronous mode, this signal is used for or for serial i/o flag 0. port d 0 ?hen configured as pd0, signal direction is controlled through the ssi1 port direction control register (prrd). the signal can be configured as ssi signal sc10 through the ssi1 port control register (pcrd). when configured as an input, this pin can tolerate 5 v. this pin is electrically disconnected internally during stop mode. sc11 pd1 input or output input or output input serial control signal 1 ?he function of sc11 is determined by the selection of either synchronous or asynchronous mode. for asynchronous mode, this signal is used for the receive clock i/o (schmitt-trigger input). for synchronous mode, this signal is used for serial i/o flag 1. port d 1 ?hen configured as pd1, signal direction is controlled through the prrd register. the signal can be configured as an ssi signal sc11 through the pcrd register. when configured as an input, this pin can tolerate 5 v. this pin is electrically disconnected internally during stop mode.
2-22 DSP56602 user? manual motorola signal/connection description synchronous serial interface 1 (ssi1) sc12 pd2 input or output input or output input serial control signal 2 ?c12 is used for frame sync i/o. sc12 is the frame sync for both the transmitter and receiver in synchronous mode, and for the transmitter only in asynchronous mode. when configured as an output, this signal is the internally generated frame sync signal. when configured as an input, this signal receives an external frame sync signal for the transmitter (and the receiver in synchronous operation). port d 2 ?hen configured as pd2, signal direction is controlled through the prrd register. the signal can be configured as an ssi signal sc12 through the pcrd register. when configured as an input, this pin can tolerate 5 v. this pin is electrically disconnected internally during stop mode. sck1 pd3 input or output input or output input serial clock ?ck1 is a bidirectional schmitt-trigger input signal providing the serial bit rate clock for the ssi. the sck1 is a clock input or output used by both the transmitter and receiver in synchronous modes, or by the transmitter in asynchronous modes. although an external serial clock can be independent of and asynchronous to the dsp system clock, it must exceed the minimum clock cycle time of 6t (i.e., the system clock frequency must be at least three times the external ssi clock frequency). the ssi needs at least three dsp phases inside each half of the serial clock. port d 3 ?hen configured as pd3, signal direction is controlled through the prrd register. the signal can be configured as an ssi signal sck1 through the pcrd register. when configured as an input, this pin can tolerate 5 v. this pin is electrically disconnected internally during stop mode. table 2-10 synchronous serial interface 1 (ssi1) (continued) signal name signal type state during reset signal description
signal/connection description synchronous serial interface 1 (ssi1) motorola DSP56602 user? manual 2-23 srd1 pd4 input input or output input serial receive data ?rd1 receives serial data and transfers the data to the ssi receive shift register. port d 4 ?hen configured as pd4, signal direction is controlled through the prrd register. the signal can be configured as an ssi signal srd1 through the pcrd register. when configured as an input, this pin can tolerate 5 v. this pin is electrically disconnected internally during stop mode. std1 pd5 input input or output input serial transmit data ?td1 is used for transmitting data from the ssi transmit shift register. port d 5 ?hen configured as pd5, signal direction is controlled through the prrd register. the signal can be configured as an ssi signal std1 through the pcrd register. when configured as an input, this pin can tolerate 5 v. this pin is electrically disconnected internally during stop mode. table 2-10 synchronous serial interface 1 (ssi1) (continued) signal name signal type state during reset signal description
2-24 DSP56602 user? manual motorola signal/connection description general purpose i/o (gpio) 2.10 general purpose i/o (gpio) three dedicated general purpose input/output (gpio) signals are provided on the DSP56602. each is reconfigurable as input, output, or tri-state. these signals are exclusively defined as gpio, and do not offer additional functionality. table 2-11 general purpose i/o (gpio) signal name signal type state during reset signal description gpio0 input or output input general purpose i/o 0 ?hen a gpio signal is used as input, the logic state is reflected to an internal register and can be read by the software. when a gpio signal is used as output, the logic state is controlled by the software. this input can tolerate 5 v. this pin is electrically disconnected internally during stop mode. gpio1 input or output input general purpose i/o 1 ?hen a gpio signal is used as input, the logic state is reflected to an internal register and can be read by the software. when a gpio signal is used as output, the logic state is controlled by the software. this input can tolerate 5 v. this pin is electrically disconnected internally during stop mode. gpio2 input or output input general purpose i/o 2 ?hen a gpio signal is used as input, the logic state is reflected to an internal register and can be read by the software. when a gpio signal is used as output, the logic state is controlled by the software. this input can tolerate 5 v. this pin is electrically disconnected internally during stop mode.
signal/connection description triple timer motorola DSP56602 user? manual 2-25 2.11 triple timer three identical and independent timers are implemented. the three timers can use internal or external clocking and can interrupt the dsp after a specified number of events (clocks), or can signal an external device after counting a specific number of internal events. when a timer port is disabled, it can be used for general purpose i/o (gpio). table 2-12 triple timer signals signal name signal type state during reset signal description tio0 input or output input or output gpio input timer 0 schmitt-trigger input/output ?hen tio0 is used as an input, the timer module functions as an external event counter or measures external pulse width or signal period. when tio0 is used as an output, the timer module functions as a timer and tio0 provides the timer pulse. when tio0 is not used by the timer module, it can be used for gpio. when configured as an input, this pin can tolerate 5 v. this pin is electrically disconnected internally during stop mode. tio1 input or output input or output gpio input timer 1 schmitt-trigger input/output ?hen tio1 is used as an input, the timer module functions as an external event counter or measures external pulse width or signal period. when tio1 is used as an output, the timer module functions as a timer and tio1 provides the timer pulse. when tio1 is not used by the timer module, it can be used for gpio. when configured as an input, this pin can tolerate 5 v. this pin is electrically disconnected internally during stop mode. tio2 input or output input or output gpio input timer 2 schmitt-trigger input/output ?hen tio2 is used as an input, the timer module functions as an external event counter or measures external pulse width or signal period. when tio2 is used as an output, the timer module functions as a timer and tio2 provides the timer pulse. when tio2 is not used by the timer module, it can be used for gpio. when configured as an input, this pin can tolerate 5 v. this pin is electrically disconnected internally during stop mode.
2-26 DSP56602 user? manual motorola signal/connection description jtag/once interface 2.12 jtag/once interface table 2-13 jtag interface/on-chip emulation module (once) signals signal name signal type state during reset signal description tck input input test clock tck is a test clock input signal used to synchronize the jtag test logic. the tck pin can be tri-stated. this input can tolerate 5 v. tdi input input test data input ?di is a test data serial input signal used for test instructions and data. tdi is sampled on the rising edge of the tck signal and has an internal pull-up resistor. this input can tolerate 5 v. tdo output tri-stated test data output ?do is a test data serial output signal used for test instructions and data. tdo is tri-stateable and is actively driven in the shift-ir and shift-dr controller states. tdo changes on the falling edge of the tck signal. tms input input test mode select ?ms is an input signal used to sequence the test controller? state machine. tms is sampled on the rising edge of the tck signal and has an internal pull-up resistor. this input can tolerate 5 v. trst input input test reset ?rst is an active-low schmitt-trigger input signal used to asynchronously initialize the test controller. trst has an internal pull-up resistor. trst must be asserted after power up. this input can tolerate 5 v. de bi- directional input debug event ?e is an open-drain bidirectional active-low signal providing, as an input, a means of entering the debug mode of operation from an external command controller, and as an output, a means of acknowledging that the chip has entered the debug mode. the de has an internal pull-up resistor. when this pin is an input, it can tolerate 5 v.
motorola DSP56602 user? manual 3-1 section 3 memory maps
3-2 DSP56602 user? manual motorola memory maps 3.1 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3-3 3.2 DSP56602 memory map description . . . . . . . . . . . . . . . .3-3 3.3 memory-mapped i/o registers. . . . . . . . . . . . . . . . . . . . .3-5
memory maps introduction motorola DSP56602 user? manual 3-3 3.1 introduction this section describes in detail the on-chip memories and the internal peripheral memory map of the DSP56602. 3.2 DSP56602 memory map description the three independent memory spaces of DSP56602: program, x data, and y data, are shown in figure 3-1 . the 34 k 24-bit prom is factory-programmed to customer specifications. sample bootstrap rom code is provided in appendix a, bootstrap program . 3.2.1 on-chip program memory the on-chip program memory consists of two blocks of memory. a 24-bit-wide, high-speed, static memory occupies the lowest locations ($0000?01ff) in the p memory space. this on-chip program ram is organized in two banks, with 256 locations in each bank. figure 3-1 DSP56602 memory map program (64 k) $ffff $0000 0.5 k internal pram external x data (64 k) y data (64 k) 34 k internal prom $9800 $ffff $0000 internal reserved (1.75 k) internal reserved $0200 $3000 $1800 $ffff internal reserved $ff80 internal x i/o internal reserved (3.5 k) $1000 4.25 k internal x data ram $0000 $1800 aa1144 $1100 6 k internal x data rom $3800 8 k internal y data rom 4.25 k internal y data ram $1100 internal reserved (1.75 k) (51.875 k) (50 k)
3-4 DSP56602 user? manual motorola memory maps DSP56602 memory map description in addition, a 24-bit-wide block of program rom occupies the locations $1000?97ff. this program rom is organized in 136 banks, with 256 locations in each bank. this memory is customer-specified and factory-programmed. note: the p memory space located at locations $0200?0fff is reserved and should not be accessed. program memory from $9800 to $ffff can be added externally and accessed through the external memory interface (port a). 3.2.2 on-chip x data memory the on-chip x data ram is a 16-bit-wide, internal, static memory occupying the lowest locations ($0000?10ff) in x memory space. the on-chip x data ram is organized in 17 banks, with 256 locations in each bank. in addition, a 16-bit-wide block of x data rom is provided in the locations $1800?2fff. this x data rom is organized in 24 banks, with 256 locations in each bank. this memory is customer-specified and factory-programmed. the on-chip peripheral registers and some of the core registers occupy the top 128 locations of the x data memory ($ff80?ffff). this area is referred to as x i/o space. it can be accessed by the move and the movep instructions, as well as by bit-oriented instructions (such as the bchg, bclr, bset, btst, brclr, brset, bsclr,bsset, jclr, jset, jsclr, and jsset instructions). note: the x memory spaces located at locations $1100?7ff and $3000?f7f are reserved and should not be accessed. 3.2.3 on-chip y data memory the on-chip y data ram is a 16-bit-wide, internal, static memory occupying the lowest locations ($0000?10ff) in x memory space. the on-chip y data ram is organized in 17 banks, with 256 locations in each bank. in addition, a 16-bit-wide block of y data rom is provided in the locations $1800?37ff. this y data rom is organized in 32 banks, with 256 locations in each bank. this memory is customer-specified and factory-programmed. note: the y memory spaces located at locations $1100?7ff and $3800?fff are reserved and should not be accessed.
memory maps memory-mapped i/o registers motorola DSP56602 user? manual 3-5 3.3 memory-mapped i/o registers all the DSP56602 on-chip peripherals are mapped on the internal x-i/o space, the top 128 locations of the x data memory space. the specific addresses for every on-chip peripheral register or peripheral-mapped register are shown in table 3-1 . table 3-1 internal i/o memory map peripheral address register name pic $ffff ipr-c?nterrupt priority register?ore $fffe ipr-p?nterrupt priority register?eripheral pll $fffd pctl0?ll control register $fffc pctl1?ll control register once $fffb ogdbr?nce gdb register biu $fffa bcr?us control register $fff9 idr?d register patch $fff8 par0?atch 0 register $fff7 par1?atch 1 register $fff6 par2?atch 2 register $fff5 par3?atch 3 register bpmr $fff4 bpmrg?us switch program memory register (24 bits) $fff3 bpmrl?us switch program memory register low (16 bits) $fff2 bpmrh?us switch program memory register high (16 bits) (reserved) $fff1 . . . $ffca (reserved)
3-6 DSP56602 user? manual motorola memory maps memory-mapped i/o registers hi08 $ffc9 hdr?i08 data register $ffc8 hddr?i08 data direction register $ffc7 htx?i08 transmit data register $ffc6 hrx?i08 receive data register $ffc5 hbar ?i08 base address register $ffc4 hpcr?i08 port control register $ffc3 hsr?i08 status register $ffc2 hcr?i08 control register (reserved) $ffc1 (reserved) $ffc0 ssi0 $ffbf pcrc?si 0 port control register $ffbe prrc?si 0 gpio direction register $ffbd pdrc?si 0 gpio data register $ffbc tx0?si 0 transmit data register $ffbb tsr0?si 0 time slot register $ffba rx0?si 0 receive data register $ffb9 ssisr0?si 0 status register $ffb8 crc0?si 0 control register c $ffb7 crb0?si 0 control register b $ffb6 cra0?si 0 control register a (reserved) $ffb5 . . . $ffb0 (reserved) ssi1 $ffaf pcrd?si 1 port control register table 3-1 internal i/o memory map (continued) peripheral address register name
memory maps memory-mapped i/o registers motorola DSP56602 user? manual 3-7 ssi1 (continued) $ffae prrd?si 1 gpio direction register $ffad pdrd?si 1 gpio data register $ffac tx1?si 1 transmit data register $ffab tsr1?si 1 time slot register $ffaa rx1?si 1 receive data register $ffa9 ssisr1?si 1 status register $ffa8 crc1?si 1 control register c $ffa7 crb1?si 1 control register b $ffa6 cra1?si 1 control register a (reserved) $ffa5 . . . $ffa0 (reserved) gpio $ff9f pcre?pio port e control register $ff9e prre?pio port e direction register $ff9d pdre?pio port e data register (reserved) $ff9c . . . $ff90 (reserved) triple timer $ff8f tcsr0?imer 0 control/status register $ff8e tlr0?imer 0 load register $ff8d tcpr0?imer 0 compare register $ff8c tcr0?imer 0 count register $ff8b tcsr1?imer 1 control/status register $ff8a tlr1?imer 1 load register table 3-1 internal i/o memory map (continued) peripheral address register name
3-8 DSP56602 user? manual motorola memory maps memory-mapped i/o registers triple timer (continued) $ff89 tcpr1?imer 1 compare register $ff88 tcr1?imer 1 count register $ff87 tcsr2?imer 2 control/status register $ff86 tlr2?imer 2 load register $ff85 tcpr2?imer 2 compare register $ff84 tcr2?imer 2 count register $ff83 tplr?imer prescaler load register $ff82 tpcr?imer prescaler count register (reserved) $ff81 (reserved) $ff80 table 3-1 internal i/o memory map (continued) peripheral address register name
motorola DSP56602 user? manual 4-1 section 4 core configuration
4-2 DSP56602 user? manual motorola core configuration 4.1 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4-3 4.2 dsp56600 core-specific attributes. . . . . . . . . . . . . . . .4-3 4.3 bootstrap program . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4-8 4.4 chip operating modes . . . . . . . . . . . . . . . . . . . . . . . . . . . .4-9 4.5 interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4-11 4.6 phase lock loop. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4-16
core configuration introduction motorola DSP56602 user? manual 4-3 4.1 introduction this section contains the core configuration details specific to the DSP56602, including descriptions of the reset operation, operating modes, interrupt vectors and registers, and phase lock loop (pll). configuration requires programming the following functional blocks: core operational control program patch detection core and peripheral interrupts bus control pll control after establishing control of these core functions, the peripherals can successfully be programmed. the DSP56602 peripherals and their programming specifics are described in subsequent sections of this document. 4.2 dsp56600 core-specific attributes the following paragraphs describe important core configuration details for the DSP56602. 4.2.1 program patch detector jump targets table 4-1 on page 4-4 lists the various jump targets for each of the four patch address registers (pars). the user can download the correct piece of code to the target location for the patch program to be executed properly. for more information on the program patch logic, see section 6, program patch logic , in the dsp56600 family manual (dsp56600fm/ad).
4-4 DSP56602 user? manual motorola core configuration dsp56600 core-specific attributes 4.2.2 operating mode register (omr) the operating mode register (omr) is a 16-bit read/write register that controls the operating mode of the DSP56602 and provides status flags on its operation. the omr is partitioned into two bytes. the least significant byte of the omr (bits 7?) is the chip operating mode (com) byte, which determines the o perating mode of the chip. the most significant byte of the omr (bits 15?) is the extended chip operating mode (eom) byte, which provides operating mode control and operating mode flags. the omr is affected only by processor reset and by instructions that directly reference it, such as the andi and ori instructions, and instructions that specify omr as a destination, such as the movec instruction. the omr is shown in figure 4-1 . 4.2.2.1 chip operating mode (md?a)?its 0? the chip operating mode (md,mc, mb, and ma) bits indicate the operating mode of the DSP56602. on processor reset, these bits are loaded from the external mode select pins, modd, modc, modb, and moda, respectively. after the DSP56602 leaves the reset state, md, mc, mb, and ma can be changed under program control. table 4-1 patch jump targets patch register patch jump target par0 $0000 par1 $0008 par2 $0010 par3 $0018 figure 4-1 operating mode register (omr) programming model * indicates reserved bits, written as 0 for future compatibility wrp eov eun xys * sd pcd ebd md mc mb ma ate * sen 11109876543210 15 14 13 12 eom com extended chip operating mode (eom) chip operating mode (com) operating mode register (omr) reset = $0000 read/write * aa1145
core configuration dsp56600 core-specific attributes motorola DSP56602 user? manual 4-5 4.2.2.2 external bus disable (edb)?it 4 the external bus disable (ebd) control bit is used to disable the external bus controller, in order to reduce the power consumption when external memories are not used. when the ebd bit is set, the external bus controller is disabled and external memory cannot be accessed. when the ebd bit is cleared, the external bus controller is enabled and external access to memory can be performed. the ebd bit is cleared on hardware reset. 4.2.2.3 pc relative logic disable (pcd)?it 5 the pc relative disable (pcd) control bit is used when pc-relative instructions (bcc, bra, lra, do, do forever, bsr, bscc, brset, brclr, bsset, or bsclr) are not in use, in order to reduce the power consumption when pc-relative instructions are not needed. when the pcd bit is set, the use of any pc-relative instruction causes undetermined results. when the pcd bit is cleared, pc-relative instructions operate correctly. in addition, when the pcd bit is set and then cleared, the use of pc-relative instructions is allowed only after seven instructions are executed. (this allows the instruction pipeline to clear.) the pcd bit is cleared on hardware reset. 4.2.2.4 stop delay (sd)?it 6 the stop delay (sd) control bit enables providing a long or short delay when exiting the stop state. the stop instruction causes the dsp56600 core to indefinitely suspend processing in the middle of the stop instruction. when the sd bit is set, a short delay of 16 clock cycles is inserted when exiting the stop state before continuing the instruction cycle. when the sd bit is cleared, a long delay of 128 k clock cycles is inserted before continuing the instruction cycle. the long delay allows a clock stabilization period for the internal clock to begin oscillating and to stabilize. when a stable external clock is used, the shorter delay allows faster start-up of the dsp56600 core. note that when the pstp bit (in the pctl1 register) is set, it overrides the sd bit and forces wake-up with no delay. the sd bit is cleared during processor reset. 4.2.2.5 xy select for stack extension (xy)?it 8 the xy select (xy) control bit for the stack extension determines whether the extension is mapped onto the x memory space or onto the y memory space. when the xy bit is set, the stack extension is mapped to the y memory space. when the xy bit is cleared, the stack extension is mapped onto the x memory space. the xy bit is cleared by hardware reset. 4.2.2.6 extended stack underflow flag (eun)?it 9 the extended stack underflow (eun) flag bit is set when a stack underflow occurs in the stack extended mode. the extended stack underflow is generated when the sp equals 0 and an additional pull operation is requested while the extended mode is enabled by the sen bit. the eun bit is a ?ticky bit?(i.e., the only way to clear this bit is by hardware reset or by an explicit move operation to the omr). the transition of the eun bit from 0 to 1 causes an interrupt priority level (ipl) level 3 stack error interrupt. the eun bit is cleared by hardware reset.
4-6 DSP56602 user? manual motorola core configuration dsp56600 core-specific attributes 4.2.2.7 extended stack overflow flag (eov)?it 10 the extended stack overflow (eov) flag bit is set when a stack overflow occurs in the stack extended mode. the extended stack overflow is generated when sp equals sz and an additional push operation is requested while the extended mode is enabled by the sen bit. the eov bit is a ?ticky bit?i.e., the only way to clear this bit is by hardware reset or by an explicit move operation to the omr). the transition of the extended stack overflow flag from 0 to 1 causes an ipl 3 stack error interrupt. the eov bit is cleared by hardware reset. 4.2.2.8 extended stack wrap flag (wr)?it 11 the extended stack wrap (wr) flag bit is set when it is first recognized that a copy from the on-chip hardware stack to the stack extension memory is needed. this flag can be used during the debugging phase of the software as means of evaluating and increasing the speed of the software implemented algorithms. the wr bit is a ?ticky bit?(i.e., the only way to clear this bit is by hardware reset or by an explicit move operation to the omr). the wr bit is cleared by hardware reset. 4.2.2.9 extended stack enable (en)?it 12 the extended stack enable (en) control bit is used to enable or to disable the stack extension in the data memory. when the en bit is set, the extension is enabled. when the en bit is cleared, the extension is disabled. the en bit is cleared by hardware reset. 4.2.2.10 address trace enable (ate)?it 15 the address trace enable (ate) bit is used for debugging purposes where internal activity should be traceable via a logic analyzer. when this bit is set, the address tracing mode is enabled and the external address bus reflects the internal program address bus for every program fetch. when this bit is cleared, normal operation resumes and the external address bus is activated only when the program address is in the external address space. the ate bit is cleared by hardware reset. 4.2.2.11 reserved bits?its 7, 13?4 bits 7, 13, and 14 are reserved for future expansion. they are read as 0 and should be written with 0 for future compatibility.
core configuration dsp56600 core-specific attributes motorola DSP56602 user? manual 4-7 4.2.3 status register (sr) the status register (sr) is a 16-bit register that consists of an 8-bit condition code register (ccr) and an 8-bit mode register (mr). the sr is stacked when program looping is initialized, when a jsr is performed, or when interrupts occur, except for no-overhead fast interrupts. the sr format is shown in figure 4-2 . understanding the interaction between the sr and the dsp56600 family instruction set is vital to understanding how to program the dsp56600 family chips. the dsp56600 family manual (dsp56600fm/ad) provides complete information on the sr. a brief description is provided in the following paragraphs. the ccr is a special-purpose control register that defines the results of previous arithmetic computations. the ccr bits are affected by data alu operations, parallel move operations, and by instructions that directly reference the ccr (such as ori and andi instructions ) or by an instruction that specifies the sr as its destination, such as the movec instruction. parallel move operations only affect the s and l bits of the ccr. during processor reset, all ccr bits are cleared. the mr is a special purpose control register that defines the current system state of the processor. the mr bits are affected by processor reset, exception processing, do, do forever, enddo, brkcc, rti, and trap instructions, and by instructions that directly reference the mr (such as the andi and ori instructions), or an instruction that specifies the sr as its destination, such as the movec instruction. during processor reset, the interrupt mask bits of the mr are set, and all the other bits are cleared. figure 4-2 status register programming model s1 s0 i1 i0 l e u n z v c lf fv 11109876543210 15 14 13 12 mr ccr rm sm s aa0712 status register (sr) reset = $0300 read/write lf?o-loop flag rm?ounding mode sm?rithmetic saturation fv?o forever flag s1?caling mode bit 1 s0?caling mode bit 0 i1?nterrupt mask bit 1 i0?nterrupt mask bit 0 s?caling bit l?imit e?xtension u?nnormalized n?egative z?ero v?verflow c?arry
4-8 DSP56602 user? manual motorola core configuration bootstrap program 4.2.4 device identification register (idr) the device identification register (idr) is a 16-bit read-only factory-programmed register used to identify the different dsp56600 core-based family members. this register specifies the derivative number and revision number. this information may be used in testing or by software. this memory-mapped register is located at $fff9. figure 4-3 shows the idr configuration, with data filled for the DSP56602. the derivative number (bits 11:0) for the DSP56602 is 011000000010. the revision number (bits 15:12) for the DSP56602 first silicon is 0001. the id register value for DSP56602 first silicon is $1602. 4.2.5 bus control register (bcr) the bus control register (bcr) specifies the number of wait states provided when using the external memory bus (also known as port a) to access external memory. the bcr allows specifying from 0 to 31 wait states. for bootstrapping, the maximum number of wait states (31) is specified by default, and can be changed under user control after bootstrapping is completed. section 5, external memory interface (port a) , provides complete details on bcr configuration. 4.3 bootstrap program on the DSP56602, the bootstrap program is developed by the customer and then factory-programmed. once programmed into the chip at the factory, it cannot be altered for customer requirements. however, a number of the bootstrap modes allow using an external location, such as an eprom or other memory, for bootstrapping. the bootstrap program can be developed to test the ma, mb, mc, and md bits in the omr to determine the bootstrap mode, and then boot from a specified port. for a listing of sample bootstrap code, see appendix a, bootstrap program . figure 4-3 DSP56602 device id register (idr) idr?:$fff9 device identification register read only 0 1 1 0 0 0 0 0 0 0 1 0 0 0 0 1 11109876543210 15 14 13 12 revision number derivative number aa1146
core configuration chip operating modes motorola DSP56602 user? manual 4-9 4.4 chip operating modes the DSP56602 operating modes determine the start-up procedure location when the chip leaves the reset state. on processor reset, the values present on the moda, modb, modc, and modd pins are loaded into the ma, mb. mc, and md bits of the omr. for more information on the omr, see operating mode register (omr) on page 4-4. the bootstrap code for the DSP56602 uses the reset addresses listed in table 4-2 to select its reset vectors and operating modes. table 4-2 DSP56602 reset addresses mode modd modc modb moda reset vector description 0 0 0 0 0 p:$c000 expanded mode (unused) 1 0 0 0 1 p:$1000 (reserved) 2 0 0 1 0 p:$1000 bootstrap from an mc68338 3 0 0 1 1 p:$1000 bootstrap from external 24-bit slow memory 4 0 1 0 0 p:$1000 bootstrap from external 8-bit slow memory 5 0 1 0 1 p:$1000 bootstrap from isa bus 6 0 1 1 0 p:$1000 bootstrap from an mc68hc11 7 0 1 1 1 p:$1000 (reserved) 8 1 0 0 0 p:$0000 expanded mode (unused) 9 1 0 0 1 p:$1000 (reserved) 10 1 0 1 0 p:$1000 bootstrap from an mc68338 11 1 0 1 1 p:$1000 bootstrap from external 24-bit slow memory 12 1 1 0 0 p:$1000 bootstrap from external 8-bit slow memory 13 1 1 0 1 p:$1000 bootstrap from isa bus 14 1 1 1 0 p:$1000 bootstrap from an mc68hc11 15 1 1 1 1 p:$1000 (reserved) note: modes 8?5 are identical to modes 0?.
4-10 DSP56602 user? manual motorola core configuration chip operating modes 4.4.1 expanded mode (mode 0) in expanded mode, the DSP56602 starts to fetch instructions beginning with the address p:$8000 from an external static ram (sram) with 31 wait states. 4.4.2 normal mode (modes 1?) in normal mode, the DSP56602 starts to fetch instructions beginning with the address p:$0400 in the internal bootstrap rom. the code programmed into the program rom tests the ma, mb, mc, and md bits in the omr to determine the exact operating mode. following completion of bootstrapping, instructions are fetched from the location determined by the values on the moda, modb, modc, and modd pins. 4.4.2.1 mode 1?eserved this mode is reserved. if this mode is selected, the DSP56602 enters an error state and is placed in a low-power mode. asserting reset causes the chip to exit the error state and perform a fresh bootstrap. 4.4.2.2 mode 2?ootstrap from mc68338 mode 2 allows loading program instructions from an mc68338 microcontroller using the hi08. 4.4.2.3 mode 3?ootstrap from 24-bit memory mode 3 allows loading program instructions from external 24-bit slow memory using port a. 4.4.2.4 mode 4?ootstrap from 8-bit memory mode 4 allows loading program instructions from external 8-bit slow memory using port a. 4.4.2.5 mode 5?ootstrap from isa bus mode 5 allows loading program instructions from an isa bus using the hi08. 4.4.2.6 mode 6?ootstrap from mc68hc11 mode 6 allows loading program instructions from an mc68hc11 microcontroller using the hi08. 4.4.2.7 mode 7?eserved this mode is reserved. it allows loading the typ2 power consumption benchmark test from the internal program rom. for more information on this benchmark application, see the DSP56602 technical data sheet (DSP56602/d) .
core configuration interrupts motorola DSP56602 user? manual 4-11 4.5 interrupts the interrupt starting address for each interrupt source is shown in table 4-3 . these addresses are located in the 256 locations of program memory pointed to by the vba (vector base address) register in the program control unit (pcu). on the DSP56602, only the vector addresses listed in table 4-3 are used for specific interrupt sources. the remaining vectors are reserved and may be used for host non-maskable interrupts (nmi), interrupt priority level (ipl) = 3, or for host command interrupt, ipl = 0?. if it is known that certain interrupts will not be used at all, those interrupt vector locations can be used for program or data storage, but this is not recommended. table 4-3 interrupt sources interrupt starting address ipl interrupt source vba:$00 3 hardware reset vba:$02 3 stack error vba:$04 3 illegal instruction vba:$06 3 debug request interrupt vba:$08 3 trap vba:$0a 3 nmi vba:$0c 3 (reserved) vba:$0e 3 (reserved) vba:$10 0? irqa vba:$12 0? irqb vba:$14 0? irqc vba:$16 0? irqd vba:$18 0? (reserved) vba:$1a 0? (reserved) vba:$1c 0? (reserved) vba:$1e 0? (reserved)
4-12 DSP56602 user? manual motorola core configuration interrupts vba:$20 0? (reserved) vba:$22 0? (reserved) vba:$24 0? timer 0 compare vba:$26 0? timer 0 overflow vba:$28 0? timer 1 compare vba:$2a 0? timer 1 overflow vba:$2c 0? timer 2 compare vba:$2e 0? timer 2 overflow vba:$30 0? ssi0 receive data vba:$32 0? ssi0 receive data with exception status vba:$34 0? ssi0 receive last slot vba:$36 0? ssi0 transmit data vba:$38 0? ssi0 transmit data with exception status vba:$3a 0? ssi0 transmit last slot vba:$3c 0? (reserved) vba:$3e 0? (reserved) vba:$40 0? ssi1 receive data vba:$42 0? ssi1 receive data with exception status vba:$44 0? ssi1 receive last slot vba:$46 0? ssi1 transmit data vba:$48 0? ssi1 transmit data with exception status vba:$4a 0? ssi0 transmit last slot vba:$4c 0? (reserved) vba:$4e 0? (reserved) table 4-3 interrupt sources (continued) interrupt starting address ipl interrupt source
core configuration interrupts motorola DSP56602 user? manual 4-13 note: any interrupt starting address (including reserved addresses) can be used for host command interrupt (ipl 0?). 4.5.1 interrupt priority levels the DSP56602 provides two interrupt priority registers, ipr-c and ipr-p. the ipr-c is dedicated for dsp56600 core interrupt sources. the ipr-p is dedicated for peripheral interrupt sources. the ipr-c and ipr-p are shown in figure 4-4 . table 4-4 and table 4-5 define the ipl bits in these registers. vba:$60 0? host receive data full vba:$62 0? host transmit data empty vba:$64 0? default host command vba:$66 0? (reserved) . . . . . . . . . vba:$fe (reserved) table 4-3 interrupt sources (continued) interrupt starting address ipl interrupt source
4-14 DSP56602 user? manual motorola core configuration interrupts note: the nmi signal (on the pinit/nmi pin) is not programmable for interrupt priority or polarity, and is always a negative-edge interrupt. figure 4-4 interrupt priority registers ipr-c and ipr-p table 4-4 interrupt priority level bits ipl bits interrupts enabled interrupt priority level xxl1 xxl0 0 0 no 0 1 yes 0 1 0 yes 1 1 1 yes 2 table 4-5 external interrupt trigger mode bits ixl2 trigger mode 0 level 1 negative edge ipr-c?:$ffff interrupt priority register?ore (ipr-c) reset = $0000 read/write icl 2 icl 1 icl 0 ibl 2 ibl 1 ibl 0 ial 2 ial 1 ial 0 * * * * 11109876543210 15 14 13 12 * indicates reserved bits, read as 0 and should be written with 0 for future compatibility irqa ipl and mode irqc ipl and mode irqb ipl and mode js5679 ipr-p?:$fffe interrupt priority register?eripheral (ipr-p) reset = $0000 read/write * * tpl 1 tpl 0 * * sil 1 sil 0 s0l 1 s0l 0 hpl 1 hpl 0 * * * * 11109876543210 15 14 13 12 timer ssi1 hi08 ipl ipl ipl ssi0 ipl aa0711 idl 2 idl 1 idl 0 irqd ipl and mode
core configuration interrupts motorola DSP56602 user? manual 4-15 4.5.2 interrupt sources priorities within an ipl if more than one interrupt request is pending when an instruction is executed, the interrupt source with the highest priority level is serviced first. when multiple interrupt requests having the same ipl are pending, a second fixed-priority structure within that ipl determines the order in which each interrupt source is serviced. the fixed priority of interrupt sources within an ipl is shown in table 4-6 . table 4-6 interrupt source priorities within an ipl priority interrupt source level 3 (non-maskable) highest hardware reset stack error illegal instruction debug request interrupt trap lowest nmi levels 0, 1, 2 (maskable) highest irqa (external interrupt) irqb (external interrupt) irqc (external interrupt) irqd (external interrupt) host command interrupt host transmit data full host receive data empty ssi0 rx data with exception interrupt ssi0 rx data interrupt ssi0 receive last slot interrupt ssi0 tx data with exception interrupt
4-16 DSP56602 user? manual motorola core configuration phase lock loop 4.6 phase lock loop the phase lock loop (pll) allows the processor to operate at a high internal clock frequency using a low frequency clock input, a feature that offers two immediate benefits: lower frequency clock input reduces the overall electromagnetic interference generated by a system. the ability to oscillate at different frequencies reduces costs by eliminating the need to add additional oscillators to a system. for more information on the pll, see section 8, pll and clock generator , in the dsp56600 family manual (dsp56600fm/ad) . ssi0 transmit last slot interrupt ssi0 tx data interrupt ssi1 rx data with exception interrupt ssi1 rx data interrupt ssi1 receive last slot interrupt ssi1 tx data with exception interrupt ssi1 transmit last slot interrupt ssi1 tx data interrupt timer 0 overflow interrupt timer 0 compare interrupt timer 1 overflow interrupt timer 1 compare interrupt timer 2 overflow interrupt lowest timer 2 compare interrupt table 4-6 interrupt source priorities within an ipl (continued) priority interrupt source
core configuration phase lock loop motorola DSP56602 user? manual 4-17 4.6.1 pll control register 0 (pctl0) the pll control register 0 (pctl0) is an x i/o-mapped 16-bit read/write register used to direct the operation of the on-chip pll. figure 4-5 shows the programming model for the pctl0 register. 4.6.1.1 multiplication factor bits (mf[11:0])?its 0?1 the multiplication factor bits (mf[11:0]) define the multiplication factor (mf) that is applied to the pll input frequency. the mf0?f11 bits are cleared during hardware reset, which corresponds to an mf of 1. table 4-7 shows how to program the mf0?f11 bits. 4.6.1.2 predivider factor bits (pd[3:0])?its 12?5 the predivider factor bits (pd[3:0]) in the pctl0 register are combined with the pd4?d6 bits in the pctl1 register to define the predivider factor (pdf) that is applied to the pll input frequency. the pd[6:0] bits are cleared during hardware reset, which corresponds to a pdf of 1. figure 4-5 pll control register 0 (pctl0) programming model table 4-7 multiplication factor bits mf[11:0] mf[11:0] multiplication factor (mf) $000 1 $001 2 $002 3 . . . . . . $ffe 4095 $fff 4096 pctl0?:$fffd pll control register 0 reset = $0000 read/write mf 11 mf 10 mf 9 mf 8 mf 7 mf 6 mf 5 mf 4 mf 3 mf 2 mf 1 mf 0 pd 3 pd 2 pd 1 pd 0 11109876543210 15 14 13 12 * indicates reserved bits, read as 0 and should be written with 0 for future compatibility aa0713
4-18 DSP56602 user? manual motorola core configuration phase lock loop 4.6.2 pll control register 1 (pctl1) the pll control register 1 (pctl1) is an x i/o-mapped 16-bit read/write register that gives additional control functions for the pll. figure 4-6 shows the programming model for the pctl1 register. 4.6.2.1 division factor (df[2:0])?its 0? the division factor (df[2:0]) bits define the division factor (df) of the low power divider. these bits specify any power-of-two division factor in the range from 2 0 to 2 7 . table 4-8 shows the programming of the df bits. changing the value of the df bits does not cause a loss of lock condition. whenever possible, changes of the operating frequency of the chip (e.g., to enter a low power mode) should be made by changing the value of the df[2:0] bits, rather than by changing the mf0?f11 bits. the df[2:0] bits are cleared by hardware reset, setting the df to divide by 1. figure 4-6 pll control register 1 (pctl1) programming model table 4-8 division factor bits df[2:0] division factor 000 2 0 001 2 1 010 2 2 011 2 3 100 2 4 101 2 5 110 2 6 111 2 7 pctl1?:$fffc pll control register 1 reset = $0000 read/write pd 6 pd 5 pd 4 * cod pen ps tp xt ld xt lr df 2 df 1 df 0 * * * * 11109876543210 15 14 13 12 * indicates reserved bits, read as 0 and should be written with 0 for future compatibility aa0714
core configuration phase lock loop motorola DSP56602 user? manual 4-19 4.6.2.2 crystal range (xtlr)?it 3 the crystal range (xtlr) bit controls the on-chip crystal oscillator transconductance. if the external crystal frequency is less than 200 khz, this bit should be set in order to decrease the transconductance of the input amplifier, otherwise the internal clocks may not be stable. if the external crystal frequency is greater than 200 khz, this bit should be cleared in order to have the full transconductance, otherwise the crystal oscillator may not function at all. changing the xtlr bit while the pll is active causes a loss of pll lock and a reinitialization of the lock process. the xtlr bit is cleared during hardware reset. 4.6.2.3 crystal disable (xtld)?it 4 the xtal disable (xtld) bit controls the on-chip crystal oscillator xtal output. when the xtld bit is set, the on-chip oscillator output is disabled. when the xtld bit is cleared, the on-chip crystal oscillator output can be used. the xtld bit is set during hardware reset. 4.6.2.4 stop processing state (pstp)?it 5 the stop processing state (pstp) bit controls the behavior of the pll and of the on-chip crystal oscillator during the stop processing state. when the pstp bit is set, the pll and the on-chip crystal oscillator remain operating while the chip is in the stop state. when the pstp bit is cleared, the pll and the on-chip crystal oscillator are disabled when the chip enters the stop state. for minimum power consumption during the stop state at the cost of longer recovery time, the pstp bit should be cleared. to enable rapid recovery when exiting the stop state, at the cost of higher power consumption, the pstp bit should be set. the pstp bit is cleared by hardware reset. 4.6.2.5 pll enable (pen)?it 6 the pll enable (pen) bit enables the pll operation. when the pen bit is set, the pll is enabled and the internal clocks are derived from the pll vco output. when the pen bit is cleared, the pll is disabled and the internal clocks are derived directly from the clock connected to the extal pin. when the pll is disabled, the vco is not operating. this helps minimize power consumption. the pen bit can be set or cleared by software any time during the chip operation. during hardware reset, this bit receives the value of the pll? pinit pin. 4.6.2.6 clock output disable (cod)?it 7 the clock output disable (cod) bit controls the output buffer of the clock at the clkout pin. when the cod bit is set, the clkout pin is held high. when the cod bit is cleared, the clkout pin is active, providing a 50% duty cycle clock synchronized to the internal core clock. if the clkout pin is not connected to external circuits, the cod bit should be set, disabling clock output and minimizing rfi noise and power dissipation. clkout oscillates in all operating states except the stop state. the cod bit is cleared by hardware reset.
4-20 DSP56602 user? manual motorola core configuration phase lock loop 4.6.2.7 predivider factor (pd[6:4])?its 9?1 the predivider factor (pd[6:4]) bits are used with the pd[3:0] bits in the pctl0 register to define the pdf that is applied to the pll input frequency. 4.6.2.8 reserved bits?its 8, 12?5 these bits are reserved and are read as 0. they should be written with 0 to ensure future compatibility.
motorola DSP56602 user? manual 5-1 section 5 external memory interface (port a)
5-2 DSP56602 user? manual motorola external memory interface (port a) 5.1 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .5-3 5.2 port a signal description . . . . . . . . . . . . . . . . . . . . . . . .5-3 5.3 port a operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .5-4 5.4 port a control and data transfer . . . . . . . . . . . . . . .5-7 5.5 program address tracing mode. . . . . . . . . . . . . . . . .5-10
external memory interface (port a) introduction motorola DSP56602 user? manual 5-3 5.1 introduction this section describes the external memory interface, also referred to as port a, and describes some of the memory transfer and trace modes associated with this interface. port a is used for program and data memory expansion. it provides an easy to use, low part-count connection with fast or slow static memories and with i/o devices. port a provides a 24-bit data bus and a 16-bit address bus capable of a sustained rate of one memory access per 2 clock cycles. external memory can be as large as 64 k 24-bit program memory space, depending on chip configuration. an internal wait state generator can be programmed to insert as many as 31 wait states if access to slower memory or i/o device is required. 5.2 port a signal description port a provides the following pins on the DSP56602. 5.2.1 address bus (a0?15) these active high outputs specify the address for external program memory accesses. to minimize power dissipation, a0?15 do not change state when external memory spaces are not being accessed. a0?15 are pulled high during hardware reset. 5.2.2 data bus (d0?23) these active high, bidirectional input/outputs provide the data bus for external program memory accesses. d0?23 are tri-stated when no external bus activity occurs, and during hardware reset. 5.2.3 memory chip select (mcs ) the memory chip select (mcs ) signal is an active low output, and is asserted when an external memory access occurs. mcs is deasserted during hardware reset.
5-4 DSP56602 user? manual motorola external memory interface (port a) port a operation 5.2.4 read enable (rd ) the read enable (rd ) signal is an active low output. rd is asserted to read external memory on the data bus (d0?23). rd is deasserted during hardware reset. 5.2.5 write enable (wr ) the write enable (wr ) signal is an active low output. wr is asserted to write external memory on the data bus (d0?23). wr is deasserted during hardware reset. 5.2.6 address trace (at ) the address trace (at ) signal is an active low output. at is asserted (for half of a clock cycle) whenever a new address is driven on the address bus (a0?15) in the program address tracing mode. the new address is either a reflection of internal fetch or internal program space move instruction or an external address driven for an external access. at is deasserted during hardware reset. 5.3 port a operation the external memory bus timing is defined by the operation of the address bus, data bus, and bus control pins. the dsp56600 core external ports are designed to interface with high-speed static ram (sram) and peripheral devices with sram-based timing, as well as with slower memory devices. 5.3.1 static ram support external memory bus timing is controlled by the bus control register (bcr). insertion of wait states is controlled by the bcr to provide constant bus access timing. the number of wait states for each external access is determined by the bcr. the external memory address is defined by the address bus. the memory chip select signal mcs is used to generate a chip select signal for the external memory device. this chip select signal changes the mode of the memory device from low power standby mode to active mode and begins the access. this allows slower memories to be used, since the mcs signal is address-based rather than read or write enable-based. srams
external memory interface (port a) port a operation motorola DSP56602 user? manual 5-5 can be easily interfaced to the dsp56600 core bus timing. because of the sram requirement to keep the address stable during the entire bus cycle, at least 1 wait state must be inserted to the bus operation. figure 5-1 shows a possible sram configuration for the DSP56602. an sram access is performed in one of the following ways: write access 1. a0?15 and mcs are asserted in the middle of clkout low phase. 2. wr is asserted with the rising edge of clkout (for a single wait state access). 3. data is driven in the middle of clkout low phase. read access 1. a0?15 and mcs are asserted in the middle of clkout low phase. 2. rd is asserted with the rising edge of clkout. 3. data is sampled in the middle of clkout last high phase of the external access. wait states postpone the disappearance of the external address, thereby increasing memory access time. in any case, sram access requires at least 1 wait state. figure 5-2 shows the memory bus operation using 1 wait state. for detailed timing specifications, see the DSP56602 technical data sheet (DSP56602/d ). figure 5-1 static ram connection diagram DSP56602 static ram a d a d mcs rd wr e g w aa1143
5-6 DSP56602 user? manual motorola external memory interface (port a) port a operation note: the assertion of the wr signal depends on the number of wait states programmed in the bcr. if a single wait state is programmed in the bcr, the wr signal is asserted with the rising edge of clkout. if the number of wait states programmed is 2 or 3, wr assertion is delayed by half cycle of clkout. if the number of wait states programmed is four or more, wr assertion is delayed by a full cycle of clkout. this feature enables the connection of slow external devices that require long address setup time before write assertion in order to prevent false write. figure 5-2 bus operation, one wait state?ram access clkout address t0 t1 t0 tw tw t1 ws data in rd data out wr t1 mcs (write) (read) bus aa0579 (data sampled at ) (data driven at )
external memory interface (port a) port a control and data transfer motorola DSP56602 user? manual 5-7 5.3.2 disabling port a because the DSP56602 provides internal memory, not all applications will require using port a. in this case, port a can be disabled completely by the user, resulting in a significant reduction in power consumption. port a can be disabled by setting the ebd bit in the operating mode register (omr). when this bit is set, the port a controller is disabled. external memory should not be accessed, otherwise improper operation may result. 5.4 port a control and data transfer two registers are used by port a for control and program memory data transfer. the bus control register (bcr) provides control functions for port a. the bus switch program memory register (bpmr) gives data transfer, and provides a special function that allows the use of 24-bit program memory accesses. 5.4.1 bus control register (bcr) port a control is provided by the bus control register (bcr). the bcr is a 16-bit read/write register used to control the external bus activity and bus interface unit operation. figure 5-3 shows the bcr programming model. 5.4.1.1 expansion bus memory wait (bmw[4:0])?its 0? the expansion bus memory wait (bmw[4:0]) control bits define the number of wait states inserted in each external sram access. the range of programmable wait states is from 0 to 31. these bits should not all be cleared, because sram memory access requires at least one wait state. figure 5-3 bus control register (bcr) programming model bcr?:$fffa bus control register reset = $001f read/write * * * * * * bmw 4 bmw 3 bmw 2 bmw 1 bmw 0 * * * * 11109876543210 15 14 13 12 * indicates reserved bits, read as 0 and should be written with 0 for future compatibility * aa07207
5-8 DSP56602 user? manual motorola external memory interface (port a) port a control and data transfer when selecting 4 to 7 wait states, one additional wait state is inserted at the end of the access. when selecting 8 or more wait states, two additional wait states are inserted at the end of the access. these trailing wait states increase the data hold time and the memory release time and do not increase the memory access time. the bmw bits are set to b11111 ($001f) during hardware reset, providing the maximum value of 31 wait states. 5.4.1.2 reserved bits?its 5?5 bits 5 through 15 in the bcr are reserved. these bits should be written as 0 to ensure future compatibility. 5.4.2 bus switch program memory register (bpmr) the bus switch program memory register (bpmr) is a 24-bit x i/o-mapped read/write register. an access to the bpmr can be either a 24-bit access or a 16-bit access. the bpmr is mapped as a 24-bit register in address bpmrg and as a pair of 16-bit registers designated as bpmr low (bpmrl) and bpmr high (bpmrh). the internal and external program memories consist of 24-bit wide words. the access to a program memory word is required in any instruction fetch and in program memory move instructions. in the latter case, the bpmr is used to interface between the internal and external program memory spaces and the rest of the dsp56600 core, which mostly consists of 16-bit components. each move from a 16-bit source to a 24-bit destination is extended by the eight lower bits of the bpmrh. each move from a 24-bit source to a 16-bit destination truncates the 24-bit source and moves only its sixteen least significant bits (lsbs). using the bpmr is the only way to access the eight most significant bits (msbs) of any program memory address, external or internal, which is essential for many applications. for example, when using a system configuration operating mode, a hardware reset causes the dsp56600 core to jump to the mask-programmed internal program memory location and execute the code fetched from this location. this code usually includes a set of program memory move instructions that load the program code to the required destination and then execute it. access to the eight msbs of each 24-bit program word is available only by using the bpmr. 5.4.2.1 bpmr mapping the bpmr is mapped as a 24-bit register in address bpmrg and as a pair of 16-bit registers in addresses x:bpmrl and x:bpmrh, respectively. the top eight bits of the bpmrh are reserved. figure 5-4 shows the bpmrl, bpmrh, and bpmrg registers.
external memory interface (port a) port a control and data transfer motorola DSP56602 user? manual 5-9 5.4.2.2 24-bit access to bpmr a 24-bit access to bpmr is done by move instruction between the bpmr and any program memory word, as shown in example 5-1 . 5.4.2.3 16-bit access to bpmr a 16-bit access to the bpmr is done either to its sixteen lsbs, which are mapped to the bpmrl, or to its eight msbs, which are mapped to the bpmrh. in both cases it is not treated as a special access but as a regular 16-bit x i/o access. reading the bpmrh clears the sixteen msbs of the 24-bit destination or the eight msbs of the 16-bit destination, depending on the destination? width. 5.4.2.4 bpmr usage typical examples a typical usage of the bpmr is for bootstrapping through external eprom or through the hi08. the following code, when loaded to an external eprom hardware reset location can load any required program ram segment. example 5-2 shows the part of it that uses the bpmr. figure 5-4 bpmr register example 5-1 move from p source address to p destination address ; move from p source address to p destination address bpmrg equ $fff4 movep p:(r0), x:bpmrg movep x:bpmrg, p:$5 x:bpmrh x:bpmrl x:bpmrg reserved bits, read as 0, should be written with 0 for future compatibility 0 23 0 15 0 15 aa0721
5-10 DSP56602 user? manual motorola external memory interface (port a) program address tracing mode a common debugging process requires the content of a segment of program memory code to be delivered to the external command controller. this information should be passed through the once global data bus register (ogdbr). the only way to pass the eight msbs of each 24-bit program word to the ogdbr register is to use the bpmr. example 5-3 shows how the ogdbr register is loaded by a 24-bit program memory word. for more information on using the once functionality, see section 10, on-chip emulation module . 5.5 program address tracing mode the address tracing (at) mode provides a means of software development in addition to the on-chip emulation (once) circuitry. section 10, on-chip emulation module , provides more information. when the at mode is enabled by setting the ate bit in the omr, the dsp56600 core reflects the addresses of internal fetches and program space moves (movem) to the address bus (a0?15), if the address bus is not needed by the dsp56600 core for external accesses. when an at cycle is performed (e.g., as an internal example 5-2 bootstrap through external eprom bpmrg equ $fff4 bpmrl equ $fff3 bpmrh equ $fff2 ;========================================================= ; this is part of the routine that loads from external eprom. ; the external eprom is 8 bit wide. do #2,_loop1 ; read the 16 lsb part of the instruction. movem p:(r2)+,a2 ; get the 8 lsb from ext. p mem. asr #8,a,a ; shift 8 bit data into a1. _loop1 ; go get another byte. movep a1,x:bpmrl ; store the 16 lsb part in bpmrl. movep p:(r2)+,x:bpmrh ; get the 8 msb part and store it in bpmrh. movep x:bpmrg,p:(r0)+ ; store 24 bit result in p mem. example 5-3 pass program memory words to the ogdbr bpmrg equ $fff4 bpmrl equ $fff3 bpmrh equ $fff2 ogdbr equ $fffb ;========================================================= movep p:(r2)+,x:bpmrg ; read the 24 bit data and store in bpmr. movep x:bpmrl,x0 ; store the 16 lsb part in x0. movep x0,x:ogdbr ; pass the 16 lsb part to ogdbr. movep x:bpmrh,y0 ; store the 8 msb part in y0. movep y0,x:ogdbr ; pass the 8 msb part to ogdbr.
external memory interface (port a) program address tracing mode motorola DSP56602 user? manual 5-11 access reflected to the address bus), the rd and wr strobes and the mcs signal are not asserted. this assures that no external device is erroneously activated. the at signal indicates that a new address is on the address bus, either of an at cycle or of an external access. the user can sample the address bus and the mcs signal with the falling edge of the at signal and sort between the at cycles and the external accesses according to the sampled value of mcs . note: the trace capability of the at mechanism differs from the once trace buffer capability. the at mechanism provides information on fetches, not on program flow. for example, in the at mechanism, fetches for a jump that is not taken are sampled, although the program flow has not gone that way. any software that interprets this information must take such aspects into account to function properly. figure 5-5 shows a possible configuration. for detailed timing information, see the DSP56602 technical data sheet (DSP56602/d) . figure 5-5 possible address tracing configuration diagram clkout address t0 t1 t0 tw tw t1 t1 bus mcs rd at at cycle external read access aa0583
5-12 DSP56602 user? manual motorola external memory interface (port a) program address tracing mode
motorola DSP56602 user? manual 6-1 section 6 gpio
6-2 DSP56602 user? manual motorola gpio 6.1 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .6-3 6.2 gpio configuration. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .6-3 6.3 gpio port e control register (pcre) . . . . . . . . . . . . .6-5 6.4 gpio port e direction register (prre) . . . . . . . . . . . .6-5 6.5 gpio port e data register (pdre) . . . . . . . . . . . . . . . . .6-6
gpio introduction motorola DSP56602 user? manual 6-3 6.1 introduction the general purpose i/o (gpio) port consists of three bidirectional pins, each pin separately controlled. functionality is controlled by the following three registers: gpio port e control register (pcre) gpio port e direction control register (prre) gpio port e data register (pdre) these registers are described in this section. this dedicated gpio port is also referred to as port e. 6.2 gpio configuration the dedicated gpio port on the DSP56602 supports three bidirectional pins. gpio functionality is also available on some of the hi08, ssi, and timer pins when these pins are not otherwise being used by their peripherals. the following registers are provided for control of the three dedicated gpio pins: pcre?pio port e control register prre?gpio port e direction control register pdre?pio port e data register on the peripherals that can be configured for gpio, the following registers are used: hi08 (port b) hpcr?ost port control register (gpio on hi08) hddr?ost data direction register (gpio on hi08) hdr?ost data register (gpio on hi08) ssi (ports c and d) pcrc?pio port c control register (gpio on ssi0) prrc?gpio port c direction control register (gpio on ssi0) pdrc?pio port c data register (gpio on ssi0) pcrd?pio port d control register (gpio on ssi1) prrd?gpio port d direction control register (gpio on ssi1) pdrd?pio port d data register (gpio on ssi1)
6-4 DSP56602 user? manual motorola gpio gpio configuration timer tcsr0?imer control/status register (gpio on the tio0 pin) tcsr1?imer control/status register (gpio on the tio1 pin) tcsr2?imer control/status register (gpio on the tio2 pin) these registers are discussed in more detail in their respective sections. the dedicated gpio programming model is shown in figure 6-1 . figure 6-1 gpio port e programming model pcre?:$ff9f port e control register reset = $0000 read/write * * * * * * * * * pc 2 pc 1 pc 0 * * * * 11109876543210 15 14 13 12 pdre?:$ff9d port e data register reset = uninitialized read/write * * * * * * * * * pd 2 pd 1 pd 0 * * * * 11109876543210 15 14 13 12 prre?:$ff9e port e direction control register reset = $0000 read/write * * * * * * * * * pdc 2 pdc 1 pdc 0 * * * * 11109876543210 15 14 13 12 * indicates reserved bits, read as 0 and should be written with 0 for future compatibility aa0701
gpio gpio port e control register (pcre) motorola DSP56602 user? manual 6-5 6.3 gpio port e control register (pcre) the 16-bit read/write gpio port e control register (pcre) controls the functionality of gpio pins. each of the pc bits controls the functionality of the corresponding port pin. when a pc bit is set, the corresponding port pin is tri-stated or gpio output with open drain defined by the direction control bit. when a pc bit is cleared, the corresponding port pin is configured as gpio pin. although the pcre has sixteen bits, only the bottom three bits are used. hardware and software reset clear all pcre bits. 6.4 gpio port e direction register (prre) the 16-bit read/write gpio port e direction register (prre) controls the direction of gpio pins. when a port pin is configured as gpio (its corresponding pc bit in the pcr is cleared), the pdc bit controls the port pin direction. when the pdc bit is set, its corresponding gpio port pin is configured as output. when the pdc bit is cleared, the gpio port pin is configured as input. when the pc bit is set and the pdc bit is cleared, the corresponding port pin is tri-stated. when both the pc bit and the pdc bit are set, the corresponding port pin is configured for open-drain gpio output. although the prr has sixteen bits, only the bottom three bits are used. hardware and software reset clear all prr bits. the following table describes the port pin configurations. table 6-1 pcre and prre bits functionality pc bit pdc bit port pin function 0 0 gpio input 0 1 gpio output 1 0 tri-stated 1 1 gpio output as open drain
6-6 DSP56602 user? manual motorola gpio gpio port e data register (pdre) 6.5 gpio port e data register (pdre) the 16-bit read/write port e data register (pdre) is used to read or write data to and from gpio pins. the pd bits are used to read or write data from and to the corresponding port pins if they are configured as gpio (by the pc bits in the pcr). if a port pin is configured as a gpio input, then the corresponding pd bit reflects the value present on this pin. if a port pin is configured as a gpio output, then the value written into the corresponding pd bit is reflected on the this pin.
motorola DSP56602 user? manual 7-1 section 7 host interface (hi08)
7-2 DSP56602 user? manual motorola host interface (hi08) 7.1 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .7-3 7.2 interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .7-3 7.3 hi08 host port . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .7-6 7.4 host interface?sp programmer? model . . . . . . .7-7 7.5 hi08?xternal host programmer? model . . . . . . .7-20 7.6 general purpose i/o . . . . . . . . . . . . . . . . . . . . . . . . . . . . .7-30
host interface (hi08) introduction motorola DSP56602 user? manual 7-3 7.1 introduction the host interface (hi08) is a byte-wide, full-duplex, double-buffered, parallel port that can be connected directly to the data bus of a host processor. the hi08 supports a variety of buses, and provides connection with a number of industry-standard dsps, microcomputers, and microprocessors without requiring any additional logic. because the host bus can operate asynchronously to the dsp core clock, the hi08 registers are divided into two banks. the host side bank is accessible to the external host, and the dsp side bank is accessible to the dsp core. the hi08 supports two classes of interfaces: host processor/mcu connection interface general purpose input/output (gpio) port unused hi08 port pins can be configured as gpio pins. 7.2 interface the following section describes the hi08 from the dsp side and from the host side. 7.2.1 dsp side eight internal x i/o-mapped locations 16-bit data word transfer modes dsp to host host to dsp host command handshaking protocols software polled interrupt driven instructions memory-mapped registers allow the standard move instruction to be used.
7-4 DSP56602 user? manual motorola host interface (hi08) interface special movep instruction provides for i/o service capability using fast interrupts. bit addressing instructions (e.g., bchg, bclr, bset, btst, jclr, jsclr, jset, jsset) simplify i/o service routines. 7.2.2 host side signals (16 pins) had[7:0] host hd7?d0 data bus or host multiplexed address/data bus had0?ad7 has/ha0 address strobe (has) or host address line ha0 ha8/ha1 host address line ha8 or host address line ha1 ha9/ha2 host address line ha9 or host address line ha2 hrw/hrd read write select (hrw) or read strobe (hrd) hds/hwr data strobe (hds) or write strobe (hwr) hcs/ha10 host chip select (hcs) or host address line ha10 hreq/htrq host request (hreq) or host transmit request (htrq) hack/hrrq host acknowledge (hack) or host receive request (hrrq) mapping consecutive byte locations memory or i/o-mapped peripheral for microprocessors, microcontrollers, etc. 8-bit data word transfer modes mixed 8- and 16-bit data transfers dsp to host host to dsp host command handshaking protocols software polled interrupt-driven
host interface (hi08) interface motorola DSP56602 user? manual 7-5 dedicated interrupts separate interrupt lines for each interrupt source special host commands force dsp core interrupts under host processor control, which are useful for: realtime production diagnostics debugging window for program development host control protocols interface capabilities interface with no additional logic to: motorola hc11 hitachi h8 8051 family thomson p6 family. interface with minimal additional logic to: isa bus motorola 68k family intel x86 family
7-6 DSP56602 user? manual motorola host interface (hi08) hi08 host port 7.3 hi08 host port this section provides a brief description of the hi08 pins and their functions. in addition to hi08 functionality, every hi08 pin can be programmed as a gpio pin when not used for hi08. table 7-1 summary of hi08 pins and operating modes hi08 port pin multiplexed address/data bus mode non multiplexed bus mode gpio mode had0?ad7 had0?ad7 hd0?d7 pb0?b7 ha0/has has/has ha0 pb8 ha1/ha8?a2/ha9 ha8?a9 ha1?a2 pb9?b10 hcs /ha10 ha10 hcs/hcs pb13 table 7-2 strobe signals support pins hi08 port pin single strobe bus dual strobe bus gpio mode hrw/hrd hrw hrd pb11 hds /hwr hds/hds hwr pb12 table 7-3 host request support pins hi08 port pin vector required no vector required gpio mode hreq /htrq hreq/hreq htrq/htrq pb14 hack /hrrq hack/hack hrrq/hrrq pb15
host interface (hi08) host interface?sp programmer? model motorola DSP56602 user? manual 7-7 figure 7-1 shows the registers in the hi08. the top row of registers (hcr, hsr, hddr, hdr, hbar, hpcr, htx, and hrx) can be accessed by the dsp core, and the bottom row of registers (isr, icr, cvr, ivr, rxh, rxl, txh, and txl) can be accessed by the host processor. 7.4 host interface?sp programmer? model the dsp56600 core views the hi08 as a memory-mapped peripheral occupying eight 16-bit words in data memory space. the dsp can use the hi08 as a normal figure 7-1 hi08 block diagram txl txh 8 hpcr latch rxl ivr cvr icr 16 hddr hcr hsr hdr dsp peripheral data bus host bus rxh hbar isr 8 hrx htx address comparator 16 16 16 16 16 16 16 16 16 8 8 8 8 3 8 8 8 8 3 5 aa0722 hcr?ost control register hsr?ost status register hpcr?ost port control register hbar?ost base address register htx?ost transmit register hrx?ost receive register hddr?ost data direction register hdr?ost data register isr?nterface status register icr?nterface control register rxl?eceive register low rxh?eceive register high txh?ransmit register high txl?ransmit register low cvr?ommand vector register ivr?nterrupt vector register
7-8 DSP56602 user? manual motorola host interface (hi08) host interface?sp programmer? model memory-mapped peripheral, using either standard polled or interrupt programming techniques. separate transmit and receive data registers are double-buffered to allow the dsp and host processor to efficiently transfer data at high speed. memory mapping allows dsp core communication with the hi08 registers to be accomplished using standard instructions and addressing modes. in addition, the movep instruction allows hi08-to-memory and memory-to-hi08 data transfers without going through an intermediate register. both hardware and software reset disable the hi08 and change the hi08 to gpio with all pins disconnected. the hi08 provides the following registers: hcr?i08 control register hsr?i08 status register htx?i08 data transmit register hrx?i08 data receive register hbar?i08 base address register hpcr?i08 port control register hddr?i08 gpio data direction register hdr?i08 gpio data register these registers can be accessed by the dsp core. they cannot be accessed by the external host processor. 7.4.1 hi08 control register (hcr) the hi08 control register (hcr) is a 16-bit read/write control register used by the dsp core to control the hi08 operating mode. reserved bits are read as 0 and should be written with 0 to ensure future compatibility. figure 7-2 shows the programming model of the hcr. the initialization values for the hcr bits are described in dsp side registers after reset on page 7-19. the hcr bits are described in the following paragraphs.
host interface (hi08) host interface?sp programmer? model motorola DSP56602 user? manual 7-9 7.4.1.1 host receive interrupt enable (hrie)?it 0 the host receive interrupt enable (hrie) bit is used to enable a dsp core interrupt when the host receive data full (hrdf) status bit in the host status register (hsr) is set. when the hrie bit is cleared, hrdf interrupts are disabled. when the hrie bit is set, a host receive data interrupt request occurs if the hrdf bit is also set. the hrie bit is cleared on hardware reset. 7.4.1.2 host transmit interrupt enable (htie)?it 1 the host transmit interrupt enable (htie) bit is used to enable a dsp core interrupt when the host transmit data empty (htde) status bit in the hsr is set. when the htie bit is cleared, htde interrupts are disabled. when the htie bit is set, a host transmit data interrupt request occurs when the htde bit is set. the htie bit is cleared on hardware reset. 7.4.1.3 host command interrupt enable (hcie)?it 2 the host command interrupt enable (hcie) bit is used to enable a dsp core interrupt when the hcp status bit in the hsr is set. when the hcie bit is cleared, hcp interrupts are disabled. when the hcie bit is set, a host command interrupt request occurs if hcp is set. the interrupt address is determined by the host command vector register (cvr). the hcie bit is cleared on hardware reset. note: host interrupt request priorities: if more than one interrupt request source is asserted and enabled (e.g., hrdf = 1, hcp = 1, hrie = 1, and hcie = 1), the hi08 generates interrupt requests according to table 7-4 . figure 7-2 host control register programming model table 7-4 hi08 interrupt request priority order priority interrupt source highest host command (hcp = 1) . . . transmit data (htde = 1) lowest receive data (hrdf = 1) hcr?:$ffc2 host control register reset = $0000 read/write * * * * * * hf3 hf2 hcie htie hrie * * * * 11109876543210 15 14 13 12 * indicates reserved bits, read as 0 and should be written with 0 for future compatibility * aa0723
7-10 DSP56602 user? manual motorola host interface (hi08) host interface?sp programmer? model 7.4.1.4 host flags 2 and 3 (hf[3:2])?its 3? the host flag 2 and host flag 3 (hf[3:2]) bits are used as general purpose flags for dsp-to-host communication. hf2 and hf3 may be set or cleared by the dsp core. hf2 and hf3 are reflected in the isr on the host side such that if they are modified by the dsp software, the host processor can read the modified values by reading the isr. these two flags are not designated for any specific purpose, but are general purpose flags. they can be used individually or as encoded pairs in a simple dsp-to-host communication protocol, implemented in both the dsp and the host processor software. 7.4.1.5 reserved bits?its 5?5 bits 5?5 in the hcr are reserved bits and are read as 0. they should be written with 0 to ensure future compatibility. 7.4.2 hi08 status register (hsr) the hi08 status register (hsr) is a 16-bit read-only status register used by the dsp to read the status and flags of the hi08. it can not be directly accessed by the host processor. reserved bits are read as 0s. the value of the hsr after reset is $0002. all bits are cleared except for the host transmit data empty (htde) bit, which is set. the hsr bits are described in the following paragraphs. 7.4.2.1 host receive data full (hrdf)?it 0 the host receive data full (hrdf) flag bit indicates that the host receive data (hrx) register contains data from the host processor. the hrdf bit is set when data is transferred from the txh:txl registers to the hrx register. the hrdf bit is cleared when the hrx register is read by the dsp core. when the hrdf bit is set, the hi08 generates a receive data full request. the hrdf bit can also be cleared by the host processor using the initialize function. the hrdf bit is cleared on hardware reset. figure 7-3 host status register (hsr) programming model hsr?:$ffc3 host status register reset = $0002 read/write * * * * * * hf1 hf0 hcp ht de hr df * * * * 11109876543210 15 14 13 12 * indicates reserved bits, read as 0 and should be written with 0 for future compatibility * aa0724
host interface (hi08) host interface?sp programmer? model motorola DSP56602 user? manual 7-11 7.4.2.2 host transmit data empty (htde)?it 1 the host transmit data empty (htde) flag bit indicates that the host transmit data (htx) register is empty and can be written by the dsp core. the htde bit is set when the htx register is transferred to the rxh:rxl registers, and cleared when htx is written by the dsp core. when the htde bit is set, the hi08 generates a transmit data full request. htde can also be set by the host processor using the initialize function. the htde bit is set on hardware reset. 7.4.2.3 host command pending (hcp)?it 2 the host command pending (hcp) flag bit reflects the status of the hc bit in the command vector register (cvr), indicating that a host command interrupt is pending. the hcp bit is set when the hc bit is set, and both bits are cleared by the hi08 hardware when the interrupt request is serviced by the dsp core. the host also can clear the hc bit, which clears the hcp bit as well. the hcp bit is cleared on hardware reset. 7.4.2.4 host flags 0 and 1 (hf[1:0])?its 3? the host flag bits (hf[1:0]) are used as a general purpose flags for host-to-dsp communication. the hf0 and hf1 bits can be set or cleared by the host. these bits reflect the status of host flags hf0 and hf1 in the icr on the host side. these two flags are not designated for any specific purpose but are general purpose flags. they can be used individually or as encoded pairs in a simple host-to-dsp communication protocol, implemented in both the dsp and the host processor software. the hf0 and hp1 bits are cleared on hardware reset. 7.4.2.5 reserved bits?its 5?5 bits 5?5 in the hsr are reserved bits and are read as 0. they should be written with 0 to ensure future compatibility.
7-12 DSP56602 user? manual motorola host interface (hi08) host interface?sp programmer? model 7.4.3 hi08 port control register (hpcr) the host port control register (hpcr) is 16-bit read/write control register used by the dsp to control the hi08 operating mode. the hpcr bits are cleared on hardware reset. note: in order to assure proper operation, the hpcr bits hap, hrp, hcsp, hdds, hmux, hasp, hdsp, hrod, haen, and hren should be changed only when the hen bit is set to 0. also, the hpcr bits should not all be written at the same time. set the hen bit only after the other bits have been written. 7.4.3.1 host gpio port enable (hgen)?it 0 the host gpio port enable (hgen) bit controls the gpio port functionality of the hi08 pins. when the hgen bit is set, pins that are configured as gpio are enabled. when this bit is cleared, pins that are configured as gpio are disconnected. outputs are tri-stated, and inputs are electrically disconnected. pins configured as hi08 are not affected. the hgen bit is cleared on hardware reset. 7.4.3.2 host address line 8 enable (ha8en)?it 1 the host address line 8 enable (ha8en) bit allows using the ha8/a1 pin for host address line 8 (ha8). when the ha8en bit is set and the hi08 is used in multiplexed bus mode, then the ha8/a1 pin is used as ha8. when the ha8en bit is cleared and the hi08 is used in multiplexed bus mode, then ha8/a1 is used as a gpio pin according to the value of hddr and hdr. when the hi08 is not in the multiplexed bus mode (hmux = 0), the ha8en bit is ignored. the ha8en bit is cleared on hardware reset. 7.4.3.3 host address line 9 enable (ha9en)?it 2 when the host address line 9 enable (ha9en) bit is set and the hi08 is used in multiplexed bus mode, the ha9/a2 pin is used as host address line 9 (ha9). when the ha9en bit is cleared and the hi08 is used in multiplexed bus mode, then the ha9/a2 pin is configured as gpio pin according to the value of hddr and hdr. when the hi08 is not in the multiplexed bus mode (hmux = 0), the ha9en bit is ignored. the ha9en bit is cleared on hardware reset. figure 7-4 host port control register (hpcr) programming model hpcr?:$ffc4 host port control register reset = $0000 read/write hm ha hd hr * hen ha hr hcs ha9 ha8 hg hap hrp hc hd 11109876543210 15 14 13 12 * indicates reserved bits, read as 0 and should be written with 0 for future compatibility sp ds ux sp sp od en en en en en en aa0725
host interface (hi08) host interface?sp programmer? model motorola DSP56602 user? manual 7-13 7.4.3.4 host chip select enable (hcsen)?it 3 when the host chip select enable (hcsen) bit is set, then hcs/a10 is used as host chip select (hcs) in the non-multiplexed bus mode (hmux = 0), and as address line 10 (ha10) in the multiplexed bus mode (hmux = 1). when this bit is cleared, the hcs/a10 pin is configured as gpio pin according to the value of hddr and hdr. the hcsen bit is cleared on hardware reset. 7.4.3.5 host request enable (hren)?it 4 the host request enable (hren) bit controls the host request pins. in the single host request mode (hdrq = 0 in the host-side interface control register (icr)), if hren is set, hreq/trq is configured as the host request (hreq) output. when the hren bit is cleared, hreq/trq and hack/rrq are configured as gpio pins according to the value of hddr and hdr. in the double host request mode (hdrq = 1 in the icr), if hren is set, hreq/trq is configured as the host transmit request (htrq) output and hack/rrq as the host receive request (hrrq) output. when the hren bit is cleared, hreq/trq and hack/rrq are configured as gpio pins according to the value of hddr and hdr. the hren bit is cleared on hardware reset. 7.4.3.6 host acknowledge enable (haen)?it 5 the host acknowledge enable (haen) bit controls the hack pin. in the single host request mode (hdrq = 0 in the icr), if haen is set and hren is set hack/rrq is configured as the host acknowledge (hack) input. when either the haen bit or the hren bit is cleared, the hack/rrq pin is configured as a gpio pin according to the value of hddr and hdr. in the double host request mode (hdrq = 1 in the icr ), haen is ignored. the haen bit is cleared on hardware reset. 7.4.3.7 host enable (hen)?it 6 the host enable (hen) bit controls the hi08 functionality. when the hen bit is set, the hi08 operates as the host interface. when the hen bit is cleared, the hi08 is not active, and all the hi08 pins are configured as gpio pins according to the value of the hddr and hdr. the hen bit is cleared on hardware reset. 7.4.3.8 reserved bit?it 7 bit 7 in the hsr is a reserved bit and is read as 0. this bit should be written with 0 to ensure future compatibility. 7.4.3.9 host request open drain (hrod)?it 8 the host request open drain (hrod) bit controls the output drive of the host request pins. in the single host request mode (hdrq = 0 in icr), if hrod is cleared and host requests are enabled (hren = 1 and hen = 1 in the host port control register (hpcr)),
7-14 DSP56602 user? manual motorola host interface (hi08) host interface?sp programmer? model the hreq pin is always driven. when the hrod bit is set and host requests are enabled, the hreq pin is an open drain output. in the double host request mode (hdrq = 1 in the icr), if hrod is cleared and host requests are enabled (hren = 1 and hen = 1 in the hpcr), the htrq and hrrq pins are always driven. when the hrod bit is set and host requests are enabled, the htrq and hrrq pins are open drain outputs. the hrod bit is cleared on hardware reset. 7.4.3.10 host data strobe polarity (hdsp)?it 9 when the host data strobe polarity (hdsp) bit is set, the data strobe pins hds or hrd and hwr are configured as active high inputs, and data is transferred when the data strobe is high. when the hdsp bit is cleared, the data strobe pins are configured as active low inputs, and data is transferred when the data strobe is low. the hdsp bit is cleared on hardware reset. 7.4.3.11 host address strobe polarity (hasp)?it 10 when the host address strobe polarity (hasp) bit is cleared, the address strobe (has) pin is an active low input, and the address on the host address/data bus is sampled when the has pin is low. when the hasp bit is set, has is an active high address strobe input, and the address on the host address/data bus is sampled when the has pin is high. the hasp bit is cleared on hardware reset. 7.4.3.12 host multiplexed bus (hmux)?it 11 when the host multiplexed bus (hmux) bit is set, the hi08 latches the lower portion of a multiplexed address/data bus. in this mode the internal address lines of the host registers are taken from the internal latch. when the hmux bit is cleared, it indicates that the hi08 is connected to a non-multiplexed type of bus, and the address lines are taken from the hi08 input pins. the hmux bit is cleared on hardware reset. 7.4.3.13 host dual data strobe (hdds)?it 12 when the host dual data strobe (hdds) bit is set, the hi08 operates in the dual strobe bus mode (i.e., a bus with separated read and write data strobes). when the hdds bit is cleared, the hi08 operates in the single strobe bus mode (i.e., a host bus with a single data strobe signal). see figure 7-5 for a description on the two types of buses. the hdds bit is cleared on hardware reset.
host interface (hi08) host interface?sp programmer? model motorola DSP56602 user? manual 7-15 7.4.3.14 host chip select polarity (hcsp)?it 13 the host chip select polarity (hcsp) bit configures the polarity of the host chip select (hcs) pin. when the hcs pin is asserted, the hi08 is selected. when the hcsp bit is set, the hcs pin is configured as an active high input and the hi08 is selected when the hcs pin is pulled high. when the hcsp bit is cleared, the hcs pin is configured as an active low input, and the hi08 is selected when the hcs pin is low. the hcsp bit is cleared on hardware reset. 7.4.3.15 host request polarity (hrp)?it 14 the host request polarity (hrp) bit controls the polarity of the host request (hreq) pin. in the single host request mode (the hdrq bit in the icr is cleared), if the hrp bit is cleared and host requests are enabled (the hren and hen bits in the hpcr are set), the hreq pin is an active low output. when the hrp bit is set and host requests are enabled, the hreq pin is active high. in the double host request mode (the hdrq bit in the icr is set), if hrp is cleared and host requests are enabled (the hren and hen bits in the hpcr are set), the htrq and hrrq pins are active low outputs. when the hrp bit is set and host requests are enabled, the htrq and hrrq pins are active high outputs. the hrp bit is cleared on hardware reset. figure 7-5 single and dual strobe bus modes hrw hds in single strobe bus mode, a ds (data-strobe) signal qualifies the access, while a r/w (read-write) signal specifies the direction of it. data hwr data hrd in dual strobe bus mode, there are special rd and wr signals that both qualify the access as being a read or a write access, respectively. read cycle write cycle write data in read data out aa0726
7-16 DSP56602 user? manual motorola host interface (hi08) host interface?sp programmer? model 7.4.3.16 host acknowledge polarity (hap)?it 15 the host acknowledge polarity (hap) bit controls the polarity of the host acknowledge (hack) pin. when the hap bit is set, the hack pin is configured as an active high input, and the hi08 outputs the contents of the ivr when the hack pin is asserted high. when the hap bit is cleared, the hack pin is configured as an active low input, and the hi08 drives the contents of the ivr onto the host bus when the hack pin is low. the hap bit is cleared on hardware reset. 7.4.4 hi08 data direction register (hddr) the hi08 data direction register (hddr) controls the direction of each of the hi08 pins configured as gpio. note that even when the hi08 is used as the host interface, some of its pins can be configured as gpio pins and the direction of these pins is controlled by this register. for more information, see general purpose i/o on page 7-30. when the drxx bit is set, the corresponding hi08 pin is configured as an output pin. when the drxx bit is cleared, the corresponding hi08 pin is configured as an input pin. 7.4.5 hi08 data register (hdr) the hi08 data register (hdr) holds the data value of the corresponding bits of the hi08 pins that are configured as gpio pins. the bit dxx functionality depends on the corresponding hddr bit. see table 7-5 . the hdr cannot be accessed by the host processor. figure 7-6 host data direction register (hddr) programming model figure 7-7 host data register (hdr) programming model hddr?:$ffc8 host data direction register reset = $0000 read/write dr dr dr dr dr dr dr dr dr dr dr dr dr dr dr dr 11109876543210 15 14 13 12 11109876543210 15 14 13 12 aa0727 hdr?:$ffc9 host data register reset = $0000 read/write 11109876543210 15 14 13 12 d11 d10 d9 d8 d7 d6 d5 d4 d3 d2 d1 d0 d15 d14 d13 d12 aa0728
host interface (hi08) host interface?sp programmer? model motorola DSP56602 user? manual 7-17 7.4.6 hi08 base address register (hbar) the hi08 base address register (hbar) is used in multiplexed bus modes. this register selects the base address for the host side registers. the address from the host is compared with the base address as programmed in the hbar, and the internal chip select is generated if a match is found. the mechanism that uses this register is shown in figure 7-8 . bits 0? provide the base address. bits 8?5 in the hbar are reserved bits and are read as 0. they should be written with 0 to ensure future compatibility. table 7-5 hdr and hddr bits functionality hddr hdr drxx dxx gpio pin non-gpio pin 0 read-only bit ?he value read is the binary value of the pin. the corresponding pin is configured as an input. read-only bit ?he bit does not contain significant data. 1 read/write bit ?he value written is the value read. the corresponding pin is configured as an output, and is driven with the data written to dxx. read/write bit ?he value written is the value read. figure 7-8 self chip select logic had[0-7] chip select comparator a[3:7] 8 bits has ha[8:10] dsp peripheral data bus aa0729 latch hbar register
7-18 DSP56602 user? manual motorola host interface (hi08) host interface?sp programmer? model 7.4.7 hi08 receive data register (hrx) the hi08 receive data (hrx) register is used for host-to-dsp data transfers. the hrx register is viewed as a 16-bit read-only register by the dsp core. the hrx register is loaded with 16-bit data from the transmit data registers (txh:txl) on the host side when both the transmit data register empty txde (host side) and dsp host receive data full (hrdf) bits are cleared. this transfer operation sets txde and hrdf. the hrx register contains valid data when the hrdf bit is set. reading hrx clears hrdf. the dsp may program the hrie bit to cause a host receive data interrupt when hrdf is set. 7.4.8 hi08 transmit data register (htx) the hi08 transmit data (htx) register is used for dsp-to-host data transfers. the htx register is viewed as a 16-bit write-only register by the dsp core. writing the htx register clears the htde bit in the hsr. the dsp can program the htie bit to cause a host transmit data interrupt when htde is set. the htx register is transferred as 16-bit data to the receive byte registers (rxh:rxl) if both the htde bit (dsp side) and receive data full (rxdf) status bits (host side) are cleared. this transfer operation sets rxdf and htde. data should not be written to the htx until htde is set to prevent the previous data from being overwritten. figure 7-9 host base address register (hbar) programming model hbar?:$ffc5 host base address register reset = $0080 read/write ba 10 ba 9 ba ba ba ba ba ba * * 11109876543210 15 14 13 12 * indicates reserved bits, read as 0 and should be written with 0 for future compatibility ***** * 876543 aa0730
host interface (hi08) host interface?sp programmer? model motorola DSP56602 user? manual 7-19 7.4.9 dsp side registers after reset table 7-6 shows the results of the four reset types on the bits in each of the hi08 registers accessible by the dsp core. 7.4.10 hi08 dsp core interrupts the hi08 may request interrupt service from either the dsp core or the host processor. the dsp core interrupts are internal and do not require the use of an external interrupt pin (see figure 7-10 ). when the appropriate interrupt enable bit in the hcr is set, an interrupt condition caused by the host processor sets the appropriate bit in the hsr, which generates an interrupt request to the dsp core. the dsp core acknowledges interrupts caused by the host processor by jumping to the appropriate interrupt service routine. the three possible interrupts are: table 7-6 dsp side registers after reset register name register data reset type hardware reset 1 software reset 2 hi08 individual reset 3 stop reset 4 hcr all bits 0 0 hpcr all bits 0 0 hsr hf[1:0] 0 0 hcp 0 0 0 0 htde 1 1 1 1 hrdf 0 0 0 0 hbar ba[10:3] $80 $80 hddr dr[15:0] 0 0 hdr d[15:0] hrx hrx[15:0] empty empty empty empty htx htx[15:0] empty empty empty empty notes: 1. caused by reset signal 2. caused by executing the reset instruction 3. caused by clearing the hen bit in the hpcr 4. caused by executing the stop instruction
7-20 DSP56602 user? manual motorola host interface (hi08) hi08?xternal host programmer? model receive data register full transmit data register empty host command the host command can access any interrupt vector in the interrupt vector table, although it has a set of vectors reserved for host command use. the dsp interrupt service routine must read or write the appropriate hi08 register (e.g., by clearing the hrdf or htde bit) to clear the interrupt. in the case of host command interrupts, the interrupt acknowledge from the dsp core program controller unit (pcu) clears the pending interrupt condition. 7.5 hi08?xternal host programmer? model the hi08 appears to the host processor as eight byte-wide registers. the host can access the hi08 asynchronously by using polling techniques or interrupt-based techniques. separate transmit and receive data registers are double-buffered to allow the dsp core and host processor to transfer data efficiently at high speed. the hi08 appears to the host processor as a memory-mapped peripheral occupying eight bytes in the host processor address space (see table 7-7 ). these registers can be figure 7-10 hsr?cr operation aa0667 15 x:hcr x:hsr 0 enable hf3 hf2 hcie htie hrie hcr hf1 hf0 hcp htde hrdf hsr status dsp core interrupts receive data full transmit data empty host command 15 0
host interface (hi08) hi08?xternal host programmer? model motorola DSP56602 user? manual 7-21 viewed as a control register (icr), a status register (isr), two data registers (rxh/txh and rxl/txl), and two vector registers (ivr and cvr). the cvr is a special command register that is used by the host processor to issue commands to the dsp. these registers can be accessed only by the host processor. host processors can use standard host processor instructions (e.g., byte move) and addressing modes to communicate with the hi08 registers. the hi08 registers are addressed so that 8-bit host processors can use 8/16-bit load and store instructions for data transfers. the hreq/htrq and hack/hrrq handshake flags are provided for polled or interrupt-driven data transfers with the host processor. because the dsp interrupt response is sufficiently fast, most host microprocessors can load or store data at their maximum programmed i/o instruction rate without testing the handshake flags for each transfer. if full handshake is not needed, the host processor can treat the dsp as a fast device, and data can be transferred between the host processor and the dsp at the fastest host processor data rate. one of the most innovative features of the host interface is the host command feature. with this feature, the host processor can issue vectored interrupt requests to the dsp core. the host can select any of 128 dsp interrupt routines to be executed by writing a vector address register in the hi08. this flexibility allows the host programmer to execute as many as 128 pre-programmed functions inside the dsp core. for example, host interrupts can allow the host processor to read or write dsp registers (x, y, or program memory locations), force interrupt handlers (e.g., ssi, sci, irqa , irqb interrupt routines), and perform control and debugging operations if interrupt routines are implemented in the dsp to perform these tasks. note: users should be aware that when the dsp core enters the stop mode, the hi08 pins are electrically disconnected internally, thus disabling the hi08 until the core leaves stop mode. while the hi08 configuration remains unchanged while in stop mode, the core cannot be restarted via the hi08. do not issue a stop command to the dsp via the hi08 unless some other mechanism for exiting stop mode is provided.
7-22 DSP56602 user? manual motorola host interface (hi08) hi08?xternal host programmer? model 7.5.1 interface control register (icr) the interface control register (icr) is an 8-bit read/write control register used by the host processor to control the hi08 interrupts and flags. the icr cannot be accessed by the dsp core. the icr is a read/write register, which allows the use of bit manipulation instructions on control register bits. the control bits are described in the following paragraphs. figure 7-11 shows the programming model of the icr. table 7-7 hi08 host side register map host address ?ig endian? hlend = 0 ?ittle endian? hlend = 1 0 icr icr interface control 1 cvr cvr command vector 2 isr isr interface status 3 ivr ivr interrupt vector 4 00000000 00000000 unused 5 00000000 00000000 unused 6 rxh/txh rxl/txl receive/transmit bytes 7 rxl/txl rxh/txh host data bus h0?7 host data bus h0?7 figure 7-11 interface control register programming model icr interface control register reset = $00 read/write init * hb hf1 hf0 hd tr rr 76543210 * indicates reserved bits, read as 0 and should be written with 0 for future compatibility end rq eq eq aa1147
host interface (hi08) hi08?xternal host programmer? model motorola DSP56602 user? manual 7-23 7.5.1.1 receive request enable (rreq)?it 0 the receive request enable (rreq) bit is used to control the hreq pin for host receive data transfers. the rreq bit is used to enable host requests via the host request (hreq or hrrq) pin when the receive data register full (rxdf) status bit in the isr is set. when the rreq bit is cleared, rxdf interrupts are disabled. when the rreq bit is set, the host request pin (hreq or hrrq) is asserted if rxdf is set. the rreq bit is cleared on hardware reset. 7.5.1.2 transmit request enable (treq)?it 1 the transmit request enable (treq) bit is used to enable host requests via the host request (hreq or htrq) pin when the transmit data register empty (txde) status bit in the isr is set. when the treq bit is cleared, txde interrupts are disabled. when the treq bit is set, the host request pin is asserted if txde is set. the treq bit is cleared on hardware reset. table 7-8 and table 7-8 summarize the effect of rreq and treq on the hreq pin. table 7-8 treq and hreq modes (hdrq = 0) treq rreq hreq pin 0 0 no interrupts (polling) 0 1 rxdf request (interrupt) 1 0 txde request (interrupt) 1 1 rxdf and txde request (interrupts) table 7-9 treq and hreq modes (hdrq = 1) treq rreq htrq pin hrrq pin 0 0 no interrupts (polling) no interrupts (polling) 0 1 no interrupts (polling) rxdf request (interrupt) 1 0 txde request (interrupt) no interrupts (polling) 1 1 txde request (interrupt) rxdf request (interrupt)
7-24 DSP56602 user? manual motorola host interface (hi08) hi08?xternal host programmer? model 7.5.1.3 double host request (hdrq)?it 2 when the double host request (hdrq) bit is set, the hreq/trq pin is configured as htrq, and the hack/rrq pin is configured as hrrq. when the hdrq bit is cleared, the hreq/trq pin is configured as hreq, and the hack/rrq is configured as hack. the hdrq bit is cleared on hardware reset. 7.5.1.4 host flag 0 (hf0)?it 3 the host flag 0 (hf0) bit is used as a general purpose flag for host-to-dsp communication. hf0 can be set or cleared by the host processor, but cannot be changed by the dsp core. hf0 is reflected in the hsr on the dsp side of the hi08. the hf0 bit is cleared on hardware reset. 7.5.1.5 host flag 1 (hf1)?it 4 the host flag 1 (hf1) bit is used as a general purpose flag for host-to-dsp communication. the hf1 bit can be set or cleared by the host processor, but can not be changed by the dsp core. the hf1 bit is reflected in the hsr on the dsp side of the hi08. the hf1 bit is cleared on hardware reset. 7.5.1.6 host little endian (hlend)?it 5 the host little endian (hlend) bit allows the hi08 to be accessed by the host in ?ittle endian?or ?ig endian?data order. when the hlend bit in the icr is set, the hi08 can be accessed by the host in ?ittle endian?order. the rxh/txh is located at address $7 and rxl/txl at $6. when the hlend bit is cleared, the hi08 can be accessed by the host in ?ig endian?host data order. the rxh/txh is located at address $6 and rxl/txl at $7. the hlend bit is cleared on hardware reset. 7.5.1.7 initialize bit (init)?it 7 the initialize (init) bit is used by the host processor to force initialization of the hi08 hardware. initialization consists of configuring the hi08 transmit and receive control bits. using the init bit to initialize the hi08 hardware may or may not be necessary, depending on the software design of the interface. the type of initialization done when the init bit is set depends on the state of treq and rreq in the hi08. the init command, which is local to the hi08, is designed to conveniently configure the hi08 into the desired data transfer mode. the commands are described in table 7-10 . the host sets the init bit, which causes the hi08 hardware to execute the init command. the interface hardware clears the init bit when the command has been executed.
host interface (hi08) hi08?xternal host programmer? model motorola DSP56602 user? manual 7-25 7.5.1.8 reserved bit?it 6 bit 6 is reserved and should be written as 0 to ensure future compatibility. 7.5.2 command vector register (cvr) the command vector register (cvr) is used by the host processor to cause the dsp core to execute an interrupt. the host command feature is independent of any of the data transfer mechanisms in the hi08. it can be used to cause any of the 128 possible interrupt routines in the dsp core to be executed. 7.5.2.1 host vector (hv[6:0])?its 0? the seven host vector (hv[6:0]) bits select the host command interrupt address to be used by the host command interrupt logic. when the host command interrupt is recognized by the dsp interrupt control logic, the address of the interrupt routine taken is 2?v. the host can write hc and hv in the same write cycle. the host processor can select any of the 128 possible interrupt routine starting addresses in the dsp by writing the interrupt routine address divided by 2 into hv[6:0]. this means that the host processor can force any of the existing interrupt handlers (ssi, irqa, irqb, etc.) and can use any of the reserved or otherwise unused addresses table 7-10 init commands treq rreq after init execution transfer direction initialized 0 0 init = 0 none 0 1 init = 0; rxdf = 0; htde = 1 dsp to host 1 0 init = 0; txde = 1; hrdf = 0 host to dsp 1 1 init = 0; rxdf = 0; htde = 1; txde = 1; hrdf = 0 host to/from dsp figure 7-12 command vector register (cvr) cvr command vector register reset = $32 read/write hc hv6 hv5 hv4 hv3 hv2 hv1 hv0 76543210 aa0732
7-26 DSP56602 user? manual motorola host interface (hi08) hi08?xternal host programmer? model provided they have been pre-programmed in the dsp. the hv[6:0] bits are set to $32 (vector location $0064) by hardware, software, individual, and stop resets. 7.5.2.2 host command bit (hc)?it 7 the host command (hc) bit is used by the host processor to handshake the execution of host command interrupts. normally, the host processor sets hc = 1 to request the host command interrupt from the dsp core. when the host command interrupt is acknowledged by the dsp core, the hc bit is cleared by the hi08 hardware. the host processor can read the state of the hc bit to determine when the host command has been accepted. after writing hc = 1 to the cvr, the host must not write to the cvr again until the hc bit is cleared by the hi08 hardware. setting the hc bit causes host command pending (hcp) to be set in the hsr. the host can write both the hc and the hv bits in the same write cycle if desired. 7.5.3 interface status register (isr) the interface status register (isr) is an 8-bit read-only status register used by the host processor to interrogate the status and flags of the hi08. the host processor can write this address without affecting the internal state of the hi08, which is useful if the user desires to access all of the hi08 registers by stepping through the hi08 addresses. the isr can be accessed by the dsp core. the status bits are described in the following paragraphs. 7.5.3.1 receive data register full (rxdf)?it 0 the receive data register full (rxdf) flag bit indicates that the receive byte registers (rxh and rxl) contain data from the dsp core and can be read by the host processor. the rxdf bit is set when the htx is transferred to the receive byte registers. rxdf is cleared when the receive data (rxl or rxh according to hlend bit) register is read by the host processor. rxdf can be cleared by the host processor using the initialize function. rxdf may be used to assert the external hreq pin if the rreq bit is set. figure 7-13 interface status register programming model isr interface status register reset = $06 read/write hr hf3 hf2 tr tx rx 76543210 * indicates reserved bits, read as 0 and should be written with 0 for future compatibility eq * * dy de df aa0733
host interface (hi08) hi08?xternal host programmer? model motorola DSP56602 user? manual 7-27 regardless of whether the rxdf interrupt is enabled, rxdf provides valid status so that polling techniques may be used by the host processor. 7.5.3.2 transmit data register empty (txde)?it 1 the transmit data register empty (txde) bit indicates that the transmit byte registers (txh, and txl) are empty and can be written by the host processor. txde is set when the transmit byte registers are transferred to the hrx register. txde is cleared when the transmit (txl or txh according to hlend bit) register is written by the host processor. txde can be set by the host processor using the initialize feature. txde may be used to assert the external hreq pin if the treq bit is set. regardless of whether the txde interrupt is enabled, txde provides valid status so that polling techniques may be used by the host processor. 7.5.3.3 transmitter ready (trdy)?it 2 the transmitter ready (trdy) flag bit indicates that txh, txl, and the hrx registers are empty. trdy = txde hrdf when the trdy bit is set, the data that the host processor writes to the txh and txl registers is immediately transferred to the dsp side of the hi08. this has many applications. for example, if the host processor issues a host command which causes the dsp core to read the hrx, the host processor can be guaranteed that the data it just transferred to the hi08 is what is being received by the dsp core. 7.5.3.4 host flag 2 (hf2)?it 3 the host flag 2 (hf2) bit in the isr indicates the state of host flag 2 in the hcr on the dsp side. the hf2 bit can only be changed by the dsp (see host flags 2 and 3 (hf[3:2])?its 3? on page 7-10). 7.5.3.5 host flag 3 (hf3)?it 4 the host flag 3 (hf3) bit in the isr indicates the state of host flag 3 in the hcr on the dsp side. the hf3 bit can only be changed by the dsp (see host flags 2 and 3 (hf[3:2])?its 3? on page 7-10). 7.5.3.6 reserved bits?its 5 and 6 bits 5 and 6 in the isr are reserved bits and are read as 0. they should be written with 0 to ensure future compatibility. 7.5.3.7 isr host request (hreq)?it 7 the isr host request (hreq) bit indicates the status of the external host request output pin (hreq) if the hdrq bit is cleared; or the external transmit and receive request output pins (htrq and hrrq, respectively) if hdrq is set.
7-28 DSP56602 user? manual motorola host interface (hi08) hi08?xternal host programmer? model when the hdrq bit is cleared: if the hreq status bit is cleared, it indicates that the host request pin (hreq) is deasserted and no host processor interrupts are being requested. if the hreq status bit is set, it means that the host request pin (hreq) is asserted, indicating that the dsp is interrupting the host processor. when the hdrq bit is set: if the hreq status bit is cleared, it indicates that the htrq and hrrq pins are deasserted and no host processor interrupts are being requested. when the hreq status bit is set, it means that the htrq pin or hrrq pin is asserted, indicating that the dsp is interrupting the host processor. the hreq bit may be set from either or both of two sources?he receive byte registers are full or the transmit byte registers are empty. these conditions are indicated by the isr rxdf and txde status bits, respectively. if the interrupt source has been enabled by the associated request enable bit in the icr, hreq is set if one or more of the two enabled interrupt sources is set. 7.5.4 interrupt vector register (ivr) the interrupt vector register (ivr) is an 8-bit read/write register that typically contains the interrupt vector number used with mc68000 family processor vectored interrupts. only the host processor can read and write this register. the contents of ivr are placed on the host data bus (h0?7) when both the hreq and hack pins are asserted. the contents of this register are initialized to a pre-defined value by a hardware or software reset, which corresponds to the uninitialized interrupt vector in the mc68000 family. 7.5.5 receive byte registers (rxh, rxl) the receive byte registers are viewed as two 8-bit read-only registers by the host processor. these registers are called receive high (rxh) and receive low (rxl). these figure 7-14 interrupt vector register (ivr) ivr interrupt vector register reset = $0f read/write iv7 iv6 iv5 iv4 iv3 iv2 iv1 iv0 76543210 aa0734
host interface (hi08) hi08?xternal host programmer? model motorola DSP56602 user? manual 7-29 two registers receive data from the high byte, and low byte, respectively, of the htx register and are selected by two external host address inputs (ha1 and ha0) during a host processor read operation. the receive byte registers contain valid data when the receive data register full (rxdf) bit is set. the host processor may program the rreq bit to assert the external hreq pin when rxdf is set. this informs the host processor that the receive byte registers are full. reading the data register at host address $7 clears the rxdf bit. when the hlend bit in the icr is cleared, the rxh is located at address $6 and rxl at $7. when the hlend bit in the icr is set, the rxh is located at address $7 and rxl at $6. 7.5.6 transmit byte registers (txh, txl) the transmit byte registers are viewed as two 8-bit write-only registers by the host processor. these registers are called transmit high (txh) and transmit low (txl). these two registers send data to the high byte and low byte, respectively, of the hrx register and are selected by two external host address inputs (ha1 and ha0) during a host processor write operation. data can be written into the transmit byte registers when the transmit data register empty (txde) bit is set. the host processor can program the treq bit to assert the external hreq pin when txde is set. this informs the host processor that the transmit byte registers are empty. writing the data register at host address $7 clears the txde bit. when the hlend bit in the icr is cleared, the txh is located at address $6 and txl at $7. when the hlend bit in the icr is set, the txh is located at address $7 and txl at $6. the transmit byte registers are transferred as 16-bit data to the hrx register when both txde and the hrdf bit are cleared. this transfer operation sets txde and hrdf. 7.5.7 host side registers after reset table 7-11 shows the result of the four kinds of reset on bits in each of the hi08 registers seen by the host processor. the hardware reset is caused by asserting the reset pin; the software reset is caused by executing the reset instruction; the individual reset is caused by clearing the hen bit in the hpcr, and the stop reset is caused by executing the stop instruction.
7-30 DSP56602 user? manual motorola host interface (hi08) general purpose i/o table 7-11 host side registers after reset 7.6 general purpose i/o when configured as general purpose i/o (gpio), the hi08 is viewed by the dsp core as memory-mapped registers that control as many as sixteen i/o pins. the software and hardware resets configure the hi08 as gpio with all sixteen pins disconnected, by clearing all dsp-side control registers. external circuitry connected to these pins may need external pull-up or pull-down resistors until the pins are configured for operation. these registers are the hi08 port control register (hpcr), the hi08 data direction register (hddr), and the hi08 data register (hdr). selection between gpio and hi08 functionality is made by clearing bits 6? in the hpcr for gpio, or setting these bits for hi08 functionality. the hddr configures each corresponding pin in the hdr as an input pin if the hddr bit is cleared or as an output pin if the hddr bit is set (see hi08 data direction register (hddr) on page 7-16 and hi08 data register (hdr) on page 7-16). register name register data reset type hardware reset software reset individual reset reset icr all bits 0 0 cvr hc 0 0 0 0 hv[6:0] $32 $32 isr hreq 0 0 1 if treq is set, 0 if treq is cleared 1 if treq is set, 0 if treq is cleared hf[3:2] 0 0 trdy 1 1 1 1 txde 1 1 1 1 rxdf 0 0 0 0 ivr iv[7:0] $0f $0f rx rxh: rxl empty empty empty empty tx txh: txl empty empty empty empty
host interface (hi08) general purpose i/o motorola DSP56602 user? manual 7-31 7.6.1 servicing the host interface the hi08 can be serviced by using one of the following protocols: polling interrupts from the host processor viewpoint, the service consists of making a data transfer since this is the only way to reset the appropriate status bits. 7.6.2 hi08 host processor data transfer the hi08 looks like static ram to the host processor. to transfer data with the hi08, the host processor must do the following: 1. assert the hi08 address to select the register to be read or written. 2. select the direction of the data transfer. 3. strobe the data transfer. 7.6.3 polling in the polling mode of operation, the hreq pin is not connected to the host processor and hack must be deasserted to insure ivr data is not being driven on h0?7 when other registers are being polled. (hack can also be configured as a gpio pin if the hack function is not required. see hi08 port control register (hpcr) on page 7-12.) the host processor first performs a data read transfer to read the isr (see figure 7-15 ) to determine, whether: 1. rxdf = 1 indicates the receive data register is full, and a data read should be performed. 2. txde = 1 indicates the transmit data register is empty, and a data write can be performed. 3. trdy = 1 indicates the transmit data register is empty and that the receive data register on the dsp side is also empty so that the data written by the host processor can be transferred directly to the dsp side.
7-32 DSP56602 user? manual motorola host interface (hi08) general purpose i/o 4. hf2 ? hf3 1 0 may indicate an application-specific state within the dsp core has been reached, which requires action on the part of the host processor. 5. when hreq = 1, the hreq pin has been asserted, and one of the previous four conditions exists. generally, after the appropriate data transfer has been made, the corresponding status bit is updated to reflect the transfer. if the host processor has issued a command to the dsp by writing the cvr and setting the hc bit, it can read the hc bit in the cvr to determine when the command has been accepted by the interrupt controller in the dsp core. when the command has been accepted for execution, the hc bit is cleared by the interrupt controller in the dsp core. 7.6.4 servicing interrupts when hreq is connected to the host processor interrupt input, the hi08 can request service from the host processor by asserting hreq. hreq is asserted when txde = 1 and/or rxdf = 1 and the corresponding enable bit (treq or rreq, respectively) is set. this is depicted in figure 7-15 . generally, servicing the interrupt starts with reading the isr to determine which dsp flag has generated the interrupt. the host processor interrupt service routine must read or write the appropriate hi08 register to clear the interrupt. hreq is deasserted when the enabled request is cleared or masked. figure 7-15 hi08 host request structure $0 hf1 hf0 hlend treq rreq icr enable 70 init 0 0 status 70 $2 hf3 hf2 trdy txde rxdf isr hreq 0 0 host request asserted hrrq hreq htrq aa0672
host interface (hi08) general purpose i/o motorola DSP56602 user? manual 7-33 the host processor interrupts are external and use the hreq pin. hreq is normally connected to the host processor maskable interrupt input. the host processor acknowledges host interrupts by executing an interrupt service routine. the two lsbs (rxdf and txde) of the isr may be tested by the host processor to determine the interrupt source (see figure 7-15 ). the host processor interrupt service routine must read or write the appropriate hi08 register to clear the interrupt. hreq is deasserted when one of the following occurs: the enabled request is cleared or masked. the dsp is reset. in the case where the host processor is a member of the mc680xx family, servicing the interrupt starts by asserting hreq to interrupt the processor. the host processor then acknowledges the interrupt by asserting hack . when hreq and hack are simultaneously asserted, the contents of the ivr are placed on the host data bus. this vector tells the host processor which routine to use to service the hreq interrupt.
7-34 DSP56602 user? manual motorola host interface (hi08) general purpose i/o
motorola DSP56602 user? manual 8-1 section 8 synchronous serial interface
8-2 DSP56602 user? manual motorola synchronous serial interface 8.1 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .8-3 8.2 ssi data and control pins . . . . . . . . . . . . . . . . . . . . . . . .8-4 8.3 ssi programming model . . . . . . . . . . . . . . . . . . . . . . . . . .8-7 8.4 operating modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .8-22
synchronous serial interface introduction motorola DSP56602 user? manual 8-3 8.1 introduction this section presents the synchronous serial interface (ssi) and discusses its architecture, programming model, operating modes, and initialization. the capabilities of the ssi include: independent (asynchronous) or shared (synchronous) transmit and receive sections with separate or shared internal/external clocks and frame syncs normal mode operation using frame sync network mode operation with as many as 32 time slots programmable word length (8, 12, or 16 bits) program options for frame synchronization and clock generation the DSP56602 provides two independent, identical ssis. (for simplicity, a single ssi is described in this section.) each ssi provides a full-duplex serial port for communication with a variety of serial devices, including one or more industry-standard codecs, other dsps, microprocessors, and peripherals that implement the motorola serial peripheral interface (spi). the ssi consists of independent transmitter and receiver sections and a common ssi clock generator. ssi pins can also be configured for use as general purpose i/o (gpio) pins when not used by the ssi. figure 8-1 shows a block diagram of the ssi. figure 8-1 ssi block diagram srd std tclk sc1 sck interrupts gdb sc0 sc2 rclk ddb cra crb tsr ssisr rx shift register rx tx0 shift register tx0 clock/frame sync generators, control logic and port control crc aa0735
8-4 DSP56602 user? manual motorola synchronous serial interface ssi data and control pins 8.2 ssi data and control pins each ssi provides the following signal connections: sc0?erial control pin 0 sc1?erial control pin 1 sc2?erial control pin 2 sck?erial clock pin srd?erial receive data pin std?erial transmit data pin 8.2.1 serial control 0 (sc0) the function of the serial control 0 (sc0) pin is determined by the selection of either synchronous or asynchronous mode (see table 8-3 on page 8-11). in asynchronous mode, this pin is used for the receive clock i/o. in synchronous mode, this pin is used for serial i/o flag 0. a typical application of flag i/o would be multiple device selection for addressing in codec systems. when this pin is configured as a serial flag pin, its direction is determined by the scd0 bit in the ssi control register c (crc) (see serial control 0 direction (scd0)?it 2 on page 8-14). when configured as an output, this pin functions either as serial output flag 0, based on control bit of0 in the ssi control register b (crb), or as a receive shift register clock output. when configured as an input, this pin is used either as serial input flag 0, which controls the if1 flag bit in the ssi status register (ssisr), or as a receive shift register clock input. the sc0 pin can be programmed as a gpio pin (pc0 on ssi0, and pd0 on ssi1) when the ssi sc0 function is not being used. 8.2.2 serial control 1 (sc1) the function of the serial control 1 (sc1) pin is determined by the selection of either synchronous or asynchronous mode (see table 8-3 on page 8-11). in asynchronous mode (such as a single codec with asynchronous transmit and receive), this pin provides the receiver frame sync i/o. in synchronous mode, this pin is used for serial i/o flag 1 and operates like the previously described sc0. the sc0 and sc1 pins provide independent serial i/o flags, but can be used together for multiple serial device selection. the sc0 and sc1 pins can be used unencoded to select either one or two
synchronous serial interface ssi data and control pins motorola DSP56602 user? manual 8-5 codecs, or can be decoded externally to select as many as four codecs. if this pin is configured as a serial flag pin, its direction is determined by the scd1 bit in the crc (see serial control 1 direction (scd1)?it 3 on page 8-14). when configured as an output, this pin provides either serial output flag 1 (based on control bit of1 ) or the receive frame sync signal. when configured as an input, this pin can be used as serial input flag 1, which controls the if1 flag bit in the ssi status register (ssisr), or as a receive frame sync from an external source. the sc1 pin can be programmed as a gpio pin (pc1 on ssi0, or pd1 on ssi1) when the ssi sc1 function is not being used. 8.2.3 serial control 2 (sc2) the serial control 2 (sc2) pin is used for frame sync i/o. the sc2 pin provides frame synchronization for both the transmitter and receiver in synchronous mode, and frame synchronization for the transmitter only in asynchronous mode (see table 8-3 on page 8-11). the direction of this pin is determined by the scd2 bit in the crc (described in serial control 2 direction (scd2)?it 4 on page 8-15). when configured as an output, this pin provides the internally generated frame sync signal. when configured as an input, this pin receives an external frame sync signal for the transmitter and the receiver in synchronous mode, and for the transmitter only in asynchronous mode. the sc2 pin can be programmed as a gpio pin (pc2 on ssi0, or pd2 on ssi1) when the ssi sc2 function is not being used. 8.2.4 serial clock (sck) the serial clock (sck) pin is a bidirectional pin that provides the serial bit rate clock for the ssi. the sck pin is a clock input or output used by the transmitter and receiver in synchronous mode, or by only the transmitter in asynchronous mode (see table 8-1 ). the sck pin can be programmed as a gpio pin (pc3 on ssi0, and pd3 on ssi1) when the ssi sck function is not being used.
8-6 DSP56602 user? manual motorola synchronous serial interface ssi data and control pins note: although an external serial clock can be independent of and asynchronous to the dsp system clock, it must exceed the minimum clock cycle time of 6t (i.e., the system clock frequency must be at least three times the external ssi clock frequency). the ssi needs at least three dsp phases (dsp phase equals t) inside each half of the serial clock. 8.2.5 serial receive data (srd) the serial receive data (srd) pin receives serial data and transfers the data to the receive shift register. the srd pin can be programmed as a gpio pin (pc4 on ssi0, and pd4 on ssi1) when the ssi srd function is not being used. 8.2.6 serial transmit data (std) the serial transmit data (std) pin is used for transmitting data from the transmit shift register. the std pin is an output when data is being transmitted from the transmit shift register. when using an internally generated bit clock, the std pin is tri-stated after transmitting the last data bit when another data word does not follow immediately. if a data word follows immediately (within a full clock cycle), the std pin is not tri-stated. the std pin can be programmed as a gpio pin (pc5 on ssi0, and pd5 on ssi1) when the ssi std function is not being used. table 8-1 ssi clock sources syn sckd scd0 receive clock source receive clock out transmit clock source transmit clock out asynchronous clock 0 0 0 ext, sc0 ext, sck 0 0 1 int sc0 ext, sck 0 1 0 ext, sc0 int sck 0 1 1 int sc0 int sck synchronous clock 1 0 d.c. ext, sck ext, sck 1 1 d.c. int sck int sck
synchronous serial interface ssi programming model motorola DSP56602 user? manual 8-7 8.3 ssi programming model the ssi contains the following registers: interface control registers cra?ontrol register a crb?ontrol register b crc?ontrol register c ssisr?si status register data registers tx?ransmit data register rx?eceive data register time slot register gpio port registers pcr?ort control register prr?ort direction register pdr?ort data register the registers described in this section represent one ssi. the DSP56602 chip has two identical ssis. when programming the ssi, the user must ensure that the correct set of registers is used for the desired ssi. the following paragraphs describe the ssi registers. 8.3.1 ssi control register a (cra) the ssi control register a (cra) is one of three 16-bit read/write control registers used to direct the operation of the ssi. the cra controls the ssi clock generator bit and frame sync rates, word length, and number of words per frame for the serial data. figure 8-2 shows the programming model for the cra. hardware and software reset clear all the bits in the cra.
8-8 DSP56602 user? manual motorola synchronous serial interface ssi programming model 8.3.1.1 prescale modulus select (pm[7:0])?its 0? the prescale modulus select (pm[7:0]) bits specify the divide ratio of the prescale divider in the ssi clock generator. a divide ratio from 1 to 256 (pm[7:0] = 0 to $ff) can be selected. the bit clock output is available on the sck pin or the sc0 pin. the bit clock output is also available internally for use as the bit clock to shift the transmit shift register and the receive shift register. careful choice of the crystal oscillator frequency and the prescaler modulus allows the industry-standard codec master clock frequencies of 2.048 mhz, 1.544 mhz, and 1.536 mhz to be generated. hardware and software reset clear the pm[7:0] bits. note: the combination psr = 1 and pm[7:0] = $00 is reserved, and may cause synchronization problems if used. 8.3.1.2 frame rate divider control (dc[4:0])?its 8?2 the frame rate divider control (dc[4:0]) bits control the divide ratio for the programmable frame rate dividers used to generate the frame clocks. in network mode, this ratio can be interpreted as the number of words per frame minus one. in normal mode, this ratio determines the word transfer rate. the divide ratio ranges from 1 to 32 (dc[4:0] = 00000 to 11111) for normal mode, and from 2 to 32 (dc[4:0] = 00001 to 11111) for network mode. in network mode, a divide ratio of 1 (dc[4:0] = 00000) is a special case (on-demand mode). in normal mode, a divide ratio of 1 (dc[4:0] = 00000) provides continuous periodic data word transfers. in this case, a bit-length sync must be used. hardware and software reset clear the dc[4:0] bits. 8.3.1.3 word length control (wl[1:0])?its 13?4 the word length control (wl[1:0]) bits are used to select the length of the data words being transferred via the ssi. word lengths of 8, 12, or 16 bits can be selected according to the assignment described in table 8-2 . hardware and software reset clear the wl1 and wl0 bits. figure 8-2 ssi control register a programming model cra0?:$ffb6 cra1?:$ffa6 ssi control register a reset = $0000 read/write dc3 dc2 dc1 dc0 pm7 pm6 pm5 pm4 pm3 pm2 pm1 pm0 psr wl1 wl0 dc4 11109876543210 15 14 13 12 aa0736
synchronous serial interface ssi programming model motorola DSP56602 user? manual 8-9 8.3.1.4 prescaler range (psr)?it 15 the prescaler range (psr) bit controls a fixed divide-by-eight prescaler in series with the variable prescaler. this bit extends the prescaler range for those cases in which a slower bit clock is desired. the minimum internally generated bit clock frequency is: fosc/2/8/256 = fosc/4096 the maximum internally generated bit clock frequency is fosc/4. when the psr bit is set, the fixed prescaler is bypassed. when the psr bit is cleared, the fixed divide-by-eight prescaler is used. hardware and software reset clear the psr bit. note: the combination psr = 1 and pm[7:0] = $00 is reserved, and may cause synchronization problems if used. 8.3.2 ssi control register b (crb) the ssi control register b (crb) is one of three 16-bit read/write control registers used to direct the operation of the ssi. the crb controls the serial output flag, the ssi interrupts enables, and transmitter and receiver enable. the crb bits are described in the following paragraphs. figure 8-3 shows the programming model for the crb. hardware and software reset clear all the bits in the crb. table 8-2 ssi word length selection wl1 wl0 number of bits per word 00 8 01 12 10 16 1 1 reserved
8-10 DSP56602 user? manual motorola synchronous serial interface ssi programming model 8.3.2.1 serial output flag 0 (of0)?it 0 when the ssi is in the synchronous mode (the syn bit in the crc is set) the sc0 pin is configured as serial i/o flag 0. when the scd0 bit in the crc is set, the sc0 pin is an output, and data present in the of0 bit is written to the sc0 pin either at the beginning of the frame in normal mode, or at the beginning of the next time slot in network mode. hardware and software reset clear the of0 bit. 8.3.2.2 serial output flag 1 (of1)?it 1 when the ssi is in the synchronous mode (the syn bit in the crc is set) the sc1 pin is configured as serial i/o flag 1. when the scd1 bit in the crc is set, the sc1 pin is an output, and data present in the of1 bit is written to the sc1 pin either at the beginning of the frame in normal mode, or at the beginning of the next time slot in network mode. hardware and software reset clear the of1 bit. hardware and software reset clear the of1 bit. the normal sequence for setting output flags when transmitting data is: 1. wait for the tde bit to be set, indicating the tx register is empty. 2. write the of0 and of1 bits flags. 3. write the transmit data to the tx register. the of0 and of1 bits are double-buffered so that the flag states appear on the pins when the tx data is transferred to the transmit shift register (i.e., the flags are synchronous with the data). note: the optional serial output pins timing (sc0 and sc1) are controlled by the frame timing and are not affected by the te or re bits. 8.3.2.3 reserved bits?its 2? bits 2? in the crb are reserved bits. they read as 0 and must be written with 0 for future compatibility. figure 8-3 ssi control register b programming model crb0?:$ffb7 crb1?:$ffa7 ssi control register b reset = $0000 read/write rie tie re te * * * * * * of1 of0 reie teie rlie tlie 11109876543210 15 14 13 12 * indicates reserved bits, read as 0 and should be written with 0 for future compatibility aa0737
synchronous serial interface ssi programming model motorola DSP56602 user? manual 8-11 8.3.2.4 transmit enable (te)?it 8 the transmit enable (te) bit enables the transfer of data from the transmit data (tx) register to the transmit shift register. when the te bit is set and a frame sync is detected, the transmit portion of the ssi is enabled for that frame. when the te bit is cleared, the transmitter is disabled after completing transmission of data currently in the transmit shift register. the std output pin is tri-stated, and any data present in the tx register is not transmitted. data can be written to the tx register when the te bit is cleared, but no data is transferred to the transmit shift register. the normal mode transmit enable sequence is to write data to the tx register (or transmit shift register) before setting the te bit. the normal transmit disable sequence is to clear the te, tie, and teie bits after the tde flag bit in the ssi status register (ssisr) is set. in the network mode, the operation of clearing and then resetting the te bit disables the transmitter after completing transmission of the current data word until the beginning of the next frame. during that time period, the std pin remains in the high-impedance state. hardware reset and software reset clear the te bit. the on-demand mode transmit enable sequence can be the same as the normal mode, or te can be left enabled. note: the te bit does not affect the generation of frame sync or output flags. table 8-3 mode and pin definition table control bits ssi pins syn te re sc0 sc1 sc2 sck std srd 000 0 0 1 rxc fsr rd 0 1 0 fst txc td 0 1 1 rxc fsr fst txc td rd 1 0 0 f0/u f1/u fs xc 1 0 1 f0/u f1/u fs xc rd 1 1 0 f0/u f1/u fs xc td 1 1 1 f0/u f1/u fs xc td rd
8-12 DSP56602 user? manual motorola synchronous serial interface ssi programming model note: a pin can be used for gpio if its corresponding bit in the port control register is cleared. 8.3.2.5 receive enable (re)?it 9 the receive enable (re) bit controls the receive portion of the ssi. when the re bit is set, the receive portion of the ssi is enabled. when the re bit is cleared, the receiver is disabled by inhibiting data transfer into the receive data (rx) register. if data is being received while the re bit is cleared, the remainder of the word is shifted in and transferred to the rx register. the re bit must be set in the normal mode and on-demand mode to receive data. in network mode, the operation of clearing re and then resetting it disables the receiver after reception of the current data word until the beginning of the next data frame. hardware and software reset clear the re bit. note: the re bit does not affect the generation of a frame sync. 8.3.2.6 transmit interrupt enable (tie)?it 10 the transmit interrupt enable (tie) control bit enables transmit interrupts. when the tie control bit and the tde flag bit in the ssisr are set, the dsp is interrupted. when the tie bit is cleared, the transmit interrupt is disabled. writing to the tx register or to the transmit shift register clears the tde bit, thus clearing the interrupt. transmit interrupts with exception have higher priority than normal transmit data interrupts. therefore, if an exception occurs (the tue bit is set) and the teie bit is set, the ssi requests an ssi transmit data with exception interrupt from the interrupt controller. hardware and software reset clear the tie bit. 8.3.2.7 receive interrupt enable (rie)?it 11 the receive interrupt enable (rie) bit enables the receive interrupt. when the rie bit is set, the dsp is interrupted when the rdf bit in the ssisr is set. when the rie bit is legend: txc rxc xc fst fsr transmitter clock receiver clock transmitter/receiver clock (synchronous operation) transmitter frame sync receiver frame sync fs td rd f0/u f1/u transmitter/receiver frame sync (synchronous operation) transmit data receive data flag 0 / unused flag 1 / unused unused (can be used as gpio pin) table 8-3 mode and pin definition table (continued) control bits ssi pins syn te re sc0 sc1 sc2 sck std srd
synchronous serial interface ssi programming model motorola DSP56602 user? manual 8-13 cleared, this interrupt is disabled. reading the rx register clears the rdf bit, thus clearing the pending interrupt. receive interrupts with exception have higher priority than normal receive data interrupts. therefore, if an exception occurs (the roe bit is set) and reie is set, the ssi requests an ssi receive data with exception interrupt from the interrupt controller. hardware and software reset clear the rie bit. 8.3.2.8 transmit last slot interrupt enable (tlie)?it 12 the transmit last slot interrupt enable (tlie) control bit enables an interrupt at the beginning of last slot of a frame in network mode. when the tlie bit is set, the dsp is interrupted at the start of the last slot in a frame in network mode. when the tlie bit is cleared, the transmit last slot interrupt is disabled. the tlie function is disabled when dc[4:0] = $0 (on-demand mode). hardware and software reset clear the tlie bit. the use of the transmit last slot interrupt is described in ssi exceptions on page 8-23. 8.3.2.9 receive last slot interrupt enable (rlie)?it 13 the receive last slot interrupt enable (rlie) control bit enables an interrupt after the last slot of a frame ended in network mode only. when the rlie bit is set, the dsp is interrupted after the last slot in a frame has ended. when the rlie bit is cleared, the receive last slot interrupt is disabled. the rlie bit is disabled when dc[4:0] = $0 (on-demand mode). hardware and software reset clear the rlie bit. the use of the receive last slot interrupt is described in ssi exceptions on page 8-23. 8.3.2.10 transmit exception interrupt enable (teie)?it 14 when the transmit exception interrupt enable (teie) control bit is set, the dsp is interrupted when both the tde and tue bits in the ssisr are set. when the teie bit is cleared, this interrupt is disabled. reading the ssisr followed by writing to the transmitter data registers clears the tue bit, thus clearing the pending interrupt. hardware and software reset clear the teie bit. 8.3.2.11 receive exception interrupt enable (reie)?it 15 when the receive exception interrupt enable (reie) control bit is set, the dsp is interrupted when both the rdf and roe bits in the ssisr are set. when the reie bit is cleared, this interrupt is disabled. reading the ssisr followed by reading the receive data register clears the roe bit, thus clearing the pending interrupt. hardware and software reset clear the reie bit. 8.3.3 ssi control register c (crc) the ssi control register c (crc) is one of three 16-bit read/write control registers used to direct the operation of the ssi. the crc controls the ssi multifunction pins, sc2, sc1,
8-14 DSP56602 user? manual motorola synchronous serial interface ssi programming model and sc0, which can be used as clock inputs or outputs, frame synchronization pins or serial i/o flag pins. the direction control bits for the serial control pins are in the crc. operating modes are also selected in this register. hardware and software reset clear all the bits in the crc. the ssi crc bits are described in the following paragraphs. figure 8-4 shows the programming model for the crc. hardware and software reset clear all the bits in the crc. 8.3.3.1 asynchronous /synchronous (syn)?it 0 the asynchronous/synchronous (syn) control bit selects whether the receive and transmit functions of the ssi occur synchronously or asynchronously with respect to each other. when the syn bit is set, synchronous mode is chosen and the transmit and receive sections use common clock and frame sync signals. when the syn bit is cleared, asynchronous mode is chosen and separate clock and frame sync signals are used for the transmit and receive sections. hardware reset and software reset clear the syn bit. 8.3.3.2 ssi mode select (mod)?it 1 the ssi mode select (mod) control bit selects the operational mode of the ssi. when the mod bit is cleared, normal mode is selected. when the mod bit is set, network mode is selected. in normal mode, the frame rate divider control (dc4?c0) bits determine the word transfer rate. one word can be transferred per frame sync during the frame sync time slot. in network mode, a word can be transferred during every time slot. hardware and software reset clear the mod bit. 8.3.3.3 serial control 0 direction (scd0)?it 2 the serial control 0 direction (scd0) control bit selects the direction of the sc0 pin. when the scd0 bit is set, the sc0 pin is an output. when the scd0 bit is cleared, the sc0 pin is an input. hardware and software reset clear the scd0 bit. 8.3.3.4 serial control 1 direction (scd1)?it 3 the serial control 1 direction (scd1) control bit selects the direction of the sc1 pin. when the scd1 bit is cleared, the sc1 pin is an input. when the scd bit 1 is set, the sc1 pin is an output. hardware and software reset clear the scd1 bit. figure 8-4 ssi control register c programming model crc0?: $ ffb8 crc1?:$ffa8 ssi control register c reset = $0000 read/write * * * * mod syn fsp fsr fs fs 11109876543210 15 14 13 12 * indicates reserved bits, read as 0 and should be written with 0 for future compatibility sc sc sh ckp sc sc l1 l0 fd kd d2 d1 d0 aa0738
synchronous serial interface ssi programming model motorola DSP56602 user? manual 8-15 8.3.3.5 serial control 2 direction (scd2)?it 4 the serial control 2 direction (scd2) control bit selects the direction of the sc2 pin. when the scd2 bit is cleared, the sc2 pin is an input. when the scd2 bit is set, the sc2 pin is an output. hardware and software reset clear the scd2 bit. 8.3.3.6 clock source direction (sckd)?it 5 the clock source direction (sckd) control bit selects the source of the clock signal used to clock the transmit shift register in the asynchronous mode and the transmit shift register and the receive shift register in the synchronous mode. when the sckd bit is set in asynchronous mode, the internal clock source becomes the bit clock for the transmit shift register and word length divider, and is the output on the sck pin. when the sckd bit is cleared, the clock source is external, the internal clock generator is disconnected from the sck pin, and an external clock source can drive the sck pin. hardware and software reset clear the sckd bit. 8.3.3.7 clock polarity (ckp)?it 6 the clock polarity (ckp) control bit controls on which bit the clock edge data and frame sync are clocked out and latched in. when the ckp bit is cleared, the data and the frame sync are clocked out on the rising edge of the transmit bit clock and latched in on the falling edge of the receive bit clock.when the ckp bit is set, the falling edge of the transmit clock is used to clock the data out and frame sync, and the rising edge of the receive clock is used to latch the data and frame sync in. hardware and software reset clear the ckp bit. 8.3.3.8 shift direction (shfd)?it 7 the shift direction (shfd) control bit causes the transmit shift register to shift data out msb first when shfd is cleared, and lsb first when shfd is set to 1. received data is shifted in msb first when shfd is cleared or lsb first when shfd equals 1. hardware and software reset clear the shfd bit. 8.3.3.9 reserved bits?its 8?1 bits 8?1 in the crc are reserved bits. they are read as 0 and should be written with 0 to ensure future compatibility. 8.3.3.10 frame sync length (fsl[1:0])?its 12?3 the frame sync length (fsl[1:0]) control bits select the length of frame sync to be generated or recognized. if fsl1 and fsl0 are both cleared, a word-length frame sync is selected for both tx and rx that is the length of the data word defined by bits wl1 and wl0. if the fsl1 bit is set and the fsl0 bit is cleared, a 1-bit clock period frame sync is selected for both tx and rx. when the fsl0 bit is set, the tx and rx frame syncs are different lengths. the fsl0 bit is ignored when the syn bit is set. encoding of the fsl1 and fsl0 bits is described in table 8-4 . hardware reset and software reset clear fsl0 and fsl1.
8-16 DSP56602 user? manual motorola synchronous serial interface ssi programming model 8.3.3.11 frame sync relative timing (fsr)?it 14 the frame sync relative timing (fsr) control bit determines the relative timing of the receive and transmit frame sync signal as referred to the serial data lines, for a word length frame sync only. when the fsr bit is set, the word length frame sync occurs one serial clock cycle earlier (i.e., together with the last bit of the previous data word). when the fsr bit is cleared, the word length frame sync occurs together with the first bit of the data word of the first slot. hardware reset and software reset clear the fsr bit. 8.3.3.12 frame sync polarity (fsp)?it 15 the frame sync polarity (fsp) bit determines the polarity of the receive and transmit frame sync signals. when fsp is set, the frame sync signal polarity is negative (i.e., the frame start is signaled by the low level of the frame sync pin). when the fsp bit is cleared, the frame sync signal polarity is positive (i.e., the frame start is signaled by the high level of the frame sync pin). hardware reset and software reset clear the fsp bit. 8.3.4 ssi status register (ssisr) the ssi status register (ssisr) is an 8-bit read-only status register used by the dsp to read the status and serial input flags of the ssi. when the ssisr is read to the internal data bus, the register contents occupy the low-order byte of the data bus, and the remaining bits are read as 0. figure 8-5 shows the programming model for the ssisr. table 8-4 fsl[1:0] encoding fsl1 fsl0 frame sync length 0 0 word-length bit clock for both tx/rx 0 1 one-bit clock for tx and word-length bit clock for rx 1 0 one-bit clock for both tx/rx 1 1 one-bit clock for rx and word-length bit clock for tx figure 8-5 ssi status register programming model ssisr0?:$ffb9 ssisr1?:$ffa9 ssi status register reset = $0040 read/write * * * * if1 if0 11109876543210 15 14 13 12 * indicates reserved bits, read as 0 and should be written with 0 for future compatibility rfs tfs rdf tde roe tue **** aa0739
synchronous serial interface ssi programming model motorola DSP56602 user? manual 8-17 8.3.4.1 serial input flag 0 (if0)?it 0 the ssi latches data present on the sc0 pin during reception of the first received bit after frame sync is detected. the if0 bit is updated with this data when the receive shift register is transferred into the rx register. the if0 bit is enabled only when the sc0 pin is programmed as ssi in the pcr, the syn bit is set, and the scd0 bit (in the crc) is cleared, indicating that sc0 is an input flag and the synchronous mode is selected. otherwise, the if0 bit reads as a 0 when it is not enabled. hardware, software, ssi individual, and stop reset clear if0. 8.3.4.2 serial input flag 1 (if1)?it 1 the ssi latches data present on the sc1 pin during reception of the first received bit after frame sync is detected.the if1 bit is updated with this data when the receive shift register is transferred into the rx register. the if1 bit is enabled only when the sc1 pin is programmed as ssi in the pcr, the syn bit is set, and the scd1 bit (in the crc) is cleared, indicating that sc1 is an input flag and synchronous mode is selected. otherwise, the if1 bit is read as 0 when it is not enabled. hardware, software, ssi individual, and stop reset clear the if1 bit. 8.3.4.3 transmit frame sync flag (tfs)?it 2 the transmit frame sync flag (tfs) bit indicates whether a transmit frame sync has occurred in the current time slot. the tfs bit is set at the start of the first time slot in the frame, and cleared during all other time slots. in network mode, data written to a transmit data register during the time slot when the tfs bit is set is transmitted( if the transmitter is enabled) during the second time slot in the frame. the tfs bit is useful in network mode to identify the start of a frame. the tfs bit is cleared by hardware, software, ssi individual, or stop reset. the tfs bit is valid only if the transmitter is enabled (the te bit in the crb is set). note: in normal mode, the tfs bit is always read as 1 when transmitting data because there is only one time slot per frame?he ?rame sync?time slot. 8.3.4.4 receive frame sync flag (rfs)?it 3 when set, the receive frame sync flag (rfs) bit indicates that a receive frame sync occurred during reception of the word in the serial receive data register. this indicates that the data word is from the first time slot in the frame. in network mode, when the rfs bit is cleared and a word is received, it indicates that the frame sync did not occur during reception of that word. the rfs bit is cleared by hardware, software, ssi individual, or stop reset. the rfs bit is valid only if the receiver is enabled by setting the re bit in the crb. note: in normal mode, the rfs bit is always read as 1 when reading data because there is only one time slot per frame?he ?rame sync?time slot.
8-18 DSP56602 user? manual motorola synchronous serial interface ssi programming model 8.3.4.5 transmitter underrun error flag (tue)?it 4 the transmitter underrun error flag (tue) bit indicates whether a transmit underrun error has occurred. the tue bit is set when the transmit shift register is empty (no new data is available to be transmitted) and a transmit time slot occurs. when a transmit underrun error occurs, the previous data, which is still present in the tx register that was not written, is retransmitted. in normal mode, a frame contains only one transmit time. in network mode, a frame can contain as many as 32 transmit time slots. if the teie bit is set, a dsp transmit underrun error interrupt request is issued when the tue bit is set. hardware, software, ssi individual, and stop reset clear the tue bit. the tue bit is also cleared by reading the ssisr with this bit set, followed by writing to the transmit data registers or to tsr. 8.3.4.6 receiver overrun error flag (roe)?it 5 the receiver overrun error flag (roe) bit indicates that a receive overrun error has occurred. the roe bit is set when the receive shift register is filled and ready to transfer to the rx register and rx is already full (i.e., rdf = 1). if the reie bit is set, a dsp receiver overrun error interrupt request is issued when the roe bit is set. hardware, software, ssi individual, and stop reset clear the roe bit. the roe bit is also cleared by reading the ssisr with this bit set, followed by reading the rx register. 8.3.4.7 transmit data register empty (tde)?it 6 the transmit data register empty (tde) bit is set when the contents of the transmit data (tx) register is transferred to the transmit shift register. this bit is also set for a tsr disabled time slot period in network mode (as if data were being transmitted after the tsr was written). when set, the tde bit indicates that data should be written to the tx register or to the time slot register (tsr). the tde bit is cleared when the dsp writes to the transmit data register, or when the dsp writes to the tsr to disable transmission of the next time slot. if the tie bit is set, a dsp transmit data interrupt request is issued when the tde bit is set. hardware, software, ssi individual, and stop reset set the tde bit. 8.3.4.8 receive data register full (rdf)?it 7 the receive data register full (rdf) bit is set when the contents of the receive shift register are transferred to the receive data register. the rdf bit is cleared when the dsp reads the ssi receive data register (rx) or cleared by hardware, software, ssi individual, or stop reset. if the rie bit (in the crb) is set, a dsp receive data interrupt request is issued when the rdf bit is set.
synchronous serial interface ssi programming model motorola DSP56602 user? manual 8-19 8.3.4.9 reserved bits?its 8?5 bits 8?5 are reserved for future use. they are read as 0 and should be written with 0 for future compatibility. 8.3.5 receive shift register the receive shift register is a 16-bit shift register that receives the incoming data from the srd pin. data is shifted in by the selected bit clock (internal or external) when the associated frame sync i/o is asserted. data is received lsb first if the shfd bit (in the crc) is set, and msb first if the shfd bit is cleared. data is transferred to the receive data register after 8, 12, or 16 serial clock cycles are counted, depending on the word length (wl1?) bits in the cra. 8.3.6 receive data register (rx) the receive data register (rx) is a 16-bit read-only register that accepts data from the receive shift register as it becomes full. the data read occupies the most significant portion of the rx register. the unused bits (least significant portion) are read as 0. if the associated interrupt is enabled, the dsp is interrupted whenever the rx register becomes full. 8.3.7 transmit shift register the transmit shift register is a 16-bit shift register that contain the data being transmitted. data is shifted out to the serial transmit data (std) pin by the selected bit clock (internal or external) when the associated frame sync i/o is asserted. depending on the word length (wl1?) bits in the cra, the number of bits shifted out before the transmit shift register is considered empty and can be written to again is 8, 12, or 16 bits. the data to be transmitted occupies the most significant portion of the shift register. the unused portion of the register is ignored. data is shifted out of this register lsb first if the shfd bit (in the crc) is set, and msb first if the shfd bit is cleared. (this is the same direction as the receive shift register.)
8-20 DSP56602 user? manual motorola synchronous serial interface ssi programming model 8.3.8 transmit data register (tx) the transmit data (tx) register is a 16-bit write-only register. data to be transmitted is written into this register and is automatically transferred to the transmit shift register. the data written (8, 12 or 16 bits) should occupy the most significant portion of the tx. the unused bits (least significant portion) of the tx register are don? care bits. if the teie bit has been enabled, the dsp is interrupted when the tx register becomes empty. 8.3.9 time slot register (tsr) the time slot register (tsr) is effectively a null data register that is used when the data is not to be transmitted in the available transmit time slot. for the purposes of timing, the tsr is a write-only register that behaves like an alternative transmit data register, except that, rather than transmitting data, the transmit data pin is in the high-impedance state for that time slot. 8.3.10 port control register (pcr) the port control register (pcr) is a 16-bit read/write register that controls the functionality of the ssi gpio pins. the pcrc is associated with ssi0. the pcrd is associated with ssi1. figure 8-6 shows the programming model for the pcr. hardware and software reset clear all pcr bits. 8.3.10.1 port control (pc[5:0])?its 0? the port control (pc[5:0]) bits control the functionality of a corresponding port pin. when a pc bit is set, the corresponding port pin is configured as a ssi pin. when a pc bit is cleared, the corresponding port pin is configured as gpio pin. figure 8-6 ssi port control register programming model pcrc?:$ffbf pcrd?:$ffaf ssi port control register reset = $0000 read/write * * * * pc1 pc0 11109876543210 15 14 13 12 * indicates reserved bits, read as 0 and should be written with 0 for future compatibility pc3 pc2 pen pc5 pc4 **** * aa0740
synchronous serial interface ssi programming model motorola DSP56602 user? manual 8-21 8.3.10.2 port enable (pen)?it 7 when the port enable (pen) control bit is set, all ssi pins are activated as defined by all other settings. when the pen bit is cleared, all ssi pins are tri-stated, ignoring all other settings. 8.3.10.3 reserved bits?its 6, 8?5 bit 6 and bits 8?5 are reserved. they are read as 0 and should be written as 0 to ensure future compatibility. 8.3.11 port direction register (prr) the port direction register (prr) is a 16-bit read/write register that controls the direction of ssi gpio pins. the prrc is associated with ssi0. the prrd is associated with ssi1. when a port pin is configured as gpio, the pdc bit controls the port pin direction. when the pdc bit is set, the gpio port pin is configured as output. when the pdc bit is cleared the gpio port pin is configured as input. hardware and software reset clear all prr bits. table 8-5 describes the port pin configurations. note: when the pen bit in the pcr is cleared, the port is disabled and all the pins are at high impedance regardless of the values of the pc and pdc bits. figure 8-7 ssi gpio direction control register programming model table 8-5 pcr and prr register bits functionality pc pdc port pin function 1 0 or 1 ssi 0 0 gpio input 0 1 gpio output prrc?:$ffbe prrd?:$ffae ssi gpio direction control register reset = $0000 read/write * * * * pd pd 11109876543210 15 14 13 12 * indicates reserved bits, read as 0 and should be written with 0 for future compatibility pd pd pd pd **** * c4 c3 c2 c1 c0 * c5 aa0741
8-22 DSP56602 user? manual motorola synchronous serial interface operating modes 8.3.12 port data register (pdr) the read/write 16-bit port data register (pdr) is used to read or write data to or from the ssi gpio pins. the pdrc is associated with ssi0, and the pdrd is associated with ssi1. bits pd[5:0] are used to read or write data to or from the corresponding port pins if they are configured as gpio (by pc[5:0] bits in the pcr). if a port pin is configured as a gpio input, then the corresponding pd bit reflects the value present on this pin. if a port pin is configured as a gpio output, then the value written into the corresponding pd bit is reflected on the this pin. hardware and software reset clear all pdr bits. 8.4 operating modes ssi operating modes are selected by the ssi control registers cra, crb, and crc. the main operating modes are described in the following paragraphs. hardware or software reset clears the port control register (pcr) and the port direction control register (prr), which configure all ssi pins to be at high impedance. the ssi is reset while all ssi pins are programmed as gpio and is active only when at least one of the ssi i/o pins is programmed as an ssi pin. the correct way to initialize the ssi is as follows: 1. hardware, software, ssi individual, or stop reset 2. program ssi control according to the desired functionality during program execution, the pc[5:0] bits in the pcr can be cleared, causing the ssi to stop serial activity and enter the individual reset state. all status bits of the interface are then set to their reset state. however, the contents of cra, crb, and crc are not affected. this procedure allows the dsp program to reset each interface separately from the other internal peripherals. during individual reset, internal accesses to the data figure 8-8 ssi gpio data register programming model pdrc?:$ffbd pdrd?:$ffad ssi gpio data register reset = $0000 read/write * * * * pd1 pd0 11109876543210 15 14 13 12 * indicates reserved bits, read as 0 and should be written with 0 for future compatibility pd3 pd2 pd5 pd4 **** * * aa0742
synchronous serial interface operating modes motorola DSP56602 user? manual 8-23 registers of the ssi are not valid and any data read will not be valid. to ensure proper operation of the interface, the dsp program must reset the ssi before changing any of its control registers except for the crb. 8.4.1 ssi exceptions the ssi generates the following exceptions , ordered from highest to lowest priority: 1. ssi receive data with exception status?his exception occurs when the receive exception interrupt is enabled, the receive data register is full, and a receiver overrun error has occurred. roe is cleared by first reading the ssisr and then reading rx. 2. ssi receive data?his exception occurs when the receive interrupt is enabled, the receive data register is full, and no receive error conditions exist. reading rx clears the pending interrupt. this error-free interrupt can use a fast interrupt service routine for minimum overhead. 3. ssi receive last slot interrupt?his exception occurs after the last slot of the frame ended (in network mode only). using the receive last slot interrupt guarantees that the previous frame was serviced with the previous setting and the new frame is to be serviced with the new setting without synchronization problems. the maximum receive last slot interrupt service time should not exceed n ?1 ssi bits service time, where n is the number of bits in a slot. 4. ssi transmit data with exception status?his exception occurs when the transmit exception interrupt is enabled, the transmit data register is empty, and a transmitter underrun error has occurred. tue is cleared by first reading the ssisr and then writing to the transmit data register, or to the tsr to clear the pending interrupt. 5. ssi transmit last slot interrupt?his exception occurs at the start of the last slot of the frame in network mode. using the transmit last slot interrupt guarantees that the previous frame was serviced with the previous setting and the new frame is to be serviced with the new setting without synchronization problems. note that the maximum transmit last slot interrupt service time should not exceed n ?1 ssi bits service time, where n is the number of bits in a slot. 6. ssi transmit data?his exception occurs when the transmit interrupt is enabled, and the transmit data register is empty, and no transmitter error conditions exist. writing to the tx registers or to the tsr clears this interrupt. this error-free interrupt can use a fast interrupt service routine for minimum overhead.
8-24 DSP56602 user? manual motorola synchronous serial interface operating modes 8.4.2 operating modes?ormal, network, and on-demand the ssi has three basic operating modes and many data/operation formats selectable by programming control bits in the cra and crc. these control bits are dc[4:0], wl1, wl0, mod, syn, fsl1, fsl0, fsr, fsp, ckp, and shfd. 8.4.2.1 operating mode selection selecting between the normal mode and network mode is accomplished by clearing or setting the mod bit in the crc. in normal mode, the ssi functions with one data word of i/o per frame. in network mode, two to 32 time slots per frame can be selected. during each frame, 0 to 32 data words of i/o can be received or transmitted. in either case, the transfers are periodic. normal mode is typically used to transfer data to or from a single device. network mode is typically used in time division multiplexed (tdm) networks of codecs or dsps with multiple words per frame. setting the mod bit in the crc, as for network mode, and setting the frame rate divider to 0 (dc[4:0] = 00000) selects the on-demand mode. this special case does not generate a periodic frame sync. instead, a frame sync pulse is generated only when data is available to transmit. the frame sync signal indicates the first time slot in the frame. the on-demand mode requires that the transmit frame sync be internal (output) and the receive frame sync be external (input). therefore, for simplex operation, the synchronous mode could be used; however, for full-duplex operation, the asynchronous mode must be used. data transmission that is data driven is enabled by writing data into the tx register. although the ssi is double-buffered, only one word can be written to the tx register, even if the transmit shift register is empty. the receive and transmit interrupts function as usual using the tde and rdf flag bits. however, transmit underruns are impossible for on-demand transmission and are disabled. this mode is useful for interfacing to codecs that require a continuous clock. 8.4.2.2 synchronous/asynchronous operating modes the transmit and receive sections of this interface can be synchronous or asynchronous?he transmitter and receiver can use common clock and synchronization signals (synchronous mode) or they can have their own separate clock and sync signals (asynchronous mode). the syn bit in the crc selects synchronous or asynchronous operation. since the ssi is designed to operate either synchronously or asynchronously, separate receive and transmit interrupts are provided. when the syn bit is cleared, the asynchronous mode is selected and the ssi tx and rx clocks and frame sync sources are independent. when the syn bit is set, the ssi tx and rx clocks and frame sync come from the same source (either external or internal). data clock and frame sync signals can be generated internally by the dsp or can be obtained from external sources. if internally generated, the ssi clock generator is used to
synchronous serial interface operating modes motorola DSP56602 user? manual 8-25 derive bit clock and frame sync signals from the dsp internal system clock. the ssi clock generator consists of a selectable fixed prescaler and a programmable prescaler for bit rate clock generation and also a programmable frame-rate divider and a word-length divider for frame-rate sync-signal generation. 8.4.2.3 frame sync selection the transmitter and receiver can operate independently of each other. the transmitter can have either a bit-long or word-long frame-sync signal format, and the receiver can have the same or opposite format. the selection is made by programming the fsl0 and fsl1 bits in the crc. 1. if the fsl1 bit is cleared, the rx frame sync is asserted during the entire data transfer period. this frame sync length is compatible with motorola codecs, spi serial peripherals, serial a/d and d/a converters, shift registers, and telecommunication pcm serial i/o. 2. if fsl1 is set, the rx frame sync pulse is active for one bit clock immediately before the data transfer period. this frame sync length is compatible with intel and national components, codecs, and telecommunication pcm serial i/o. the ability to mix frame sync lengths is useful in configuring systems in which data is received from one type device (e.g., codec) and transmitted to a different type device. the fsl0 bit controls whether rx and tx have the same frame sync length. if fsl0 equals 0, rx and tx have the same frame sync length, which is selected by fsl1. if fsl0 equals 1, rx and tx have different frame sync lengths, which are selected by fsl1. fsl0 is ignored when the syn bit is set. the fsr bit controls the relative timing of the word length frame sync as referred to the data word. when the fsr bit is cleared, the word length frame sync is generated (or expected) with the first bit of the data word. when the fsr bit is set, the word length frame sync is generated (or expected) with the last bit of the previous word. the fsr bit is ignored when a bit length frame sync is selected. the fsp bit controls the polarity of the frame sync. when fsp is cleared the polarity of the frame sync is positive (i.e., the frame sync signal is asserted high). when fsp is set the polarity of the frame sync is negative (i.e., the frame sync is asserted low.) the ssi receiver looks for a receive frame sync leading edge (or trailing edge, if fsp is set) only when the previous frame is completed. if the frame sync goes high before the frame is completed (or before the last bit of the frame is received in the case of a bit frame sync or a word length frame sync with fsr set), the current frame sync is not recognized, and the receiver is internally disabled until the next frame sync. frames do not have to be adjacent?hat is, a new frame sync does not have to immediately follow the previous
8-26 DSP56602 user? manual motorola synchronous serial interface operating modes frame. gaps of arbitrary periods can occur between frames. the transmitter is tri-stated during these gaps. 8.4.2.4 shift direction selection some data formats, such as those used by codecs, specify msb first. other data formats, such as the aes-ebu digital audio, specify lsb first. to interface with devices from both systems, the shift registers in the ssi are bidirectional. the msb/lsb selection is made by programming the shfd bit in the crc. when the shfd bit is cleared, data is shifted into the receive shift register and shifted out of the transmit shift register msb first. if the shfd bit is set, data is shifted into the receive shift register and shifted out of the transmit shift register lsb first. 8.4.3 serial i/o flags two ssi pins (sc1 and sc0) are available as serial i/o flags. their operation is controlled by the syn, scd0, and scd1 bits in the crc. the control bits (of1 and of0) and status bits (if1 and if0) are double-buffered to and from the sc1 and sc0 pins. double-buffering the flags keeps them synchronized with tx and rx registers. the flags are only available in the synchronous mode (when the syn bit is set). each flag can be separately programmed. when flag 0 is enabled, its direction is selected by scd0, scd0 = 1 as output and scd0 = 0 as input. in the same way when flag1 is enabled, its direction is selected by scd1, scd1 = 1 as output and scd1 = 0 as input. when programmed as input, the sc0 and sc1 pins are latched at the same time the first bit of the receive data word is sampled. since the input is latched, the signal on the input flag pins sc0 and sc1 can change without affecting the input flag until the first bit of the next received data word. when the received data word is latched by the rx register, the latched values are then latched by the if0 and if1 bits (in the ssisr) and can be read by software. when programmed as output, the sc0 and sc1 pins are driven by the value from the of0 and of1 bits (in the crb) and latched when the contents of the tx register is transferred to the transmit shift register. the values on the sc0 and sc1 pins are stable from the same time the first bit of the transmit data word is transmitted until the first bit of the next transmit data word is transmitted. software can change the values of the of0 and of1 bits (in the crb), thus controlling the sc0 and sc1 pin values for each transmitted word.
motorola DSP56602 user? manual 9-1 section 9 triple timer module
9-2 DSP56602 user? manual motorola triple timer module 9.1 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .9-3 9.2 triple timer module architecture . . . . . . . . . . . . . . .9-3 9.3 timer architecture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .9-4 9.4 triple timer module programming model. . . . . . . . .9-6 9.5 timer modes of operation . . . . . . . . . . . . . . . . . . . . . . .9-13
triple timer module introduction motorola DSP56602 user? manual 9-3 9.1 introduction this section describes the triple timer module, composed of a common 14-bit prescaler and three independent and identical general purpose 16-bit timer/event counters, each with its own memory-mapped register set. each timer can use internal or external clocking and can interrupt the dsp after a specified number of events (clocks) or can signal an external device after counting internal events. each timer connects to the external world through one bidirectional pin, tio. when the tio pin is configured as an input, the timer functions as an external event counter or measures external pulse width/signal period. when the tio pin is used as an output, the timer functions as either a timer, a watchdog, or a pulse width modulator (pwm) . when the tio pin is not used by the timer, it can be configured as a general purpose i/o (gpio) pin. 9.2 triple timer module architecture the triple timer module includes a 16-bit timer prescaler load register (tplr), a 16-bit timer prescaler count register (tpcr), a 14-bit prescaler counter, and three timers. each one of the three timers can use the prescaler clock as its clock source. the timer prescaler load register (tplr) is a 16-bit read/write register that controls the prescaler divide factor and the source for the prescaler input clock. the timer prescaler count register (tpcr) is a 16-bit read-only register that reflects the current value in the prescaler counter. the register bits are described in the following paragraphs. the 14-bit prescaler counter is decremented on each rising edge of the prescaler input clock pulse. the counter is enabled when at least one of the three timers is both enabled and is using the prescaler output as its source. figure 9-1 shows a block diagram of the triple timer module.
9-4 DSP56602 user? manual motorola triple timer module timer architecture 9.3 timer architecture figure 9-2 shows a block diagram of a timer. it includes a 16-bit counter, a 16-bit read/write timer control and status register (tcsr), a 16-bit read only timer count register (tcr), a 16-bit write only timer load register (tlr), a 16-bit read/write timer compare register (tcpr), and logic for clock selection and interrupt generation. the dsp views each timer as a memory-mapped peripheral occupying four 16-bit words in the x data memory space. the user can use standard polled or interrupt programming techniques. the programming model is shown in figure 9-3 on page 9-6. figure 9-1 triple timer module block diagram timer prescaler count register gdb 16 16 tplr 16 timer 0 timer 2 timer 1 14-bit prescaler clk/2 tio0 tio1 tio2 tpcr timer prescaler load register 16 aa0743 counter
triple timer module timer architecture motorola DSP56602 user? manual 9-5 figure 9-2 16-bit timer module block diagram gdb control/status register tcsr counter timer interrupt timer control clk/2 tio compare register tcpr = 16 16 logic load register count register tlr prescaled clk tcr aa0744 16 16 9 2 16 16 16 16 16
9-6 DSP56602 user? manual motorola triple timer module triple timer module programming model 9.4 triple timer module programming model the registers comprising the triple timer module are shown in figure 9-3 . figure 9-3 triple timers programming model tcsr0?:$ff8f tcsr1?:$ff8b tcsr2?:$ff87 timer control/status register reset = $0000 read/write di dir trm inv tc3 tc2 tc0 tcie toie te pce do 11109876543210 15 14 13 12 tcr0?:$ff8c tcr1?:$ff88 tcr2?:$ff84 timer count register reset = $0000 read only count register 1110987654321 15 14 13 12 * indicates reserved bits, read and written as 0 to ensure future compatibility tpcr?:$ff82 timer prescaler count register reset = uninitialized read only pc7 pc6 pc4 pc3 pc2 pc1 pc0 * 11109876543210 15 14 13 12 * tcf tof tc1 * tcpr0?:$ff8d tcpr1?:$ff89 tcpr2?:$ff85 timer compare register reset = uninitialized read/write compare register 11109876543210 15 14 13 12 tplr?:$ff83 timer prescaler load register reset = $0000 read/write pl7 pl6 pl4 pl3 pl2 pl1 pl0 11109876543210 15 14 13 12 pl5 pl pl pl pl9 pl8 pl ps1 ps0 pc pc pc pc pc9 pc5 pc8 13 12 11 10 13 12 11 10 aa0745 tlr0?:$ff8e tlr1?:$ff8a tlr2?:$ff86 timer load register reset = uninitialized write only load register 11109876543210 15 14 13 12
triple timer module triple timer module programming model motorola DSP56602 user? manual 9-7 9.4.1 timer prescaler load register (tplr) the timer prescaler load register (tplr) is a 16-bit read/write register that controls the prescaler divide factor and the source for the prescaler input clock. the control bits are described in the following paragraphs. 9.4.1.1 prescaler preload value (pl[13:0])?its 0?3 the prescaler preload value bits (pl[13:0]) contain the prescaler preload value. this preload value is loaded into the prescaler counter whenever either the counter reaches the value of 0 or the counter switches state from disabled to enabled. for pl[13:0] = n, the prescaler counts n + 1 source clock cycles before generating a prescaled clock pulse. therefore, the prescaler divide factor is the preload value + 1. the pl[13:0] bits are cleared by hardware and software reset . 9.4.1.2 prescaler source (ps[1:0])?its 14?5 the prescaler source (ps[1:0]) bits control the source of the prescaler clock. table 9-1 summarizes the functionality of the ps bits. the dsp internal clock clk divided by two is selected when the ps[1:0] bits are cleared. the other combinations select one of the tio pins as the source clock for the prescaler, regardless of the operating mode of the selected timer. notes: 1. if the prescaler source clock is external, the prescaler counter is incremented by the transitions on the tio pin. the external clock is internally synchronized to the internal clock and its frequency should be lower than the dsp internal clock (clk) divided by 4. 2. to ensure proper functionality, the ps[1:0] bits should be changed only when the prescaler counter is disabled. the ps[1:0] bits are cleared by hardware and software reset. table 9-1 ps[1:0] bit functionality ps1 ps0 prescaler clock source 0 0 dsp internal clock (clk) divided by two 0 1 tio0 1 0 tio1 1 1 tio2
9-8 DSP56602 user? manual motorola triple timer module triple timer module programming model 9.4.2 timer prescaler count register (tpcr) the timer prescaler count register (tpcr) is a 16-bit read-only register that reflects the current value in the prescaler counter. the register bits are described in the following paragraphs. 9.4.2.1 prescaler counter value (pc[13:0])?its 0?3 the prescaler counter value (pc[13:0]) bits contain the current value in the prescaler counter. 9.4.2.2 reserved bits?its 14?5 these reserved bits are read as 0. 9.4.3 timer count register (tcr) the timer count register (tcr) is a 16-bit read-only register. in timer and watchdog modes, the counter contents can be read at any time by reading the tcr. in measurement modes, the tcr is loaded with the current value of the counter on the appropriate edge of the input signal and its value can be read to determine the width, period, or delay of the leading edge of the input signal (incoming on the tio pin). 9.4.4 timer load register (tlr) the timer load register (tlr) is a 16-bit write-only register. in all modes, the counter is preloaded with the tlr value after the timer enable (te) bit in the tcsr is set and a first event occurs. in timer modes, if the timer reload mode (trm) bit is set, the counter is reloaded each time after it has reached the value contained by the timer compare register (tcr) and the new event occurs. in measurement modes, if the trm bit is set, the counter is reloaded with the tlr value on each appropriate edge of the input signal, after the timer enable (te) bit is set. in pulse width modulation (pwm) modes, if the trm bit is set, the counter is reloaded each time after it has overflowed and the new event occurs. in watchdog modes, if the trm bit is set, the counter is reloaded each time after it has reached the value contained by the timer compare register and the new event occurs. in this mode, the counter is also reloaded whenever the tlr is written with a new value while the te bit is set. in all modes, if the trm bit is cleared, the counter operates as free running counter.
triple timer module triple timer module programming model motorola DSP56602 user? manual 9-9 9.4.5 timer compare register (tcpr) the timer compare register (tcpr) is a 16-bit read/write register that contains the value to be compared to the counter value. the counter value is compared against the value in the tcpr on every timer clock after the timer enable (te) bit is set. when the compare matches, the tcf bit is set. if interrupts are enabled (the tcie bit is set), an interrupt is also generated. in measurement modes, the tcpr is ignored. 9.4.6 timer control/status register (tcsr) the timer control/status register (tcsr) is a 16-bit read/write register that controls the timer and reflects its status. the control and status bits are described in the following paragraphs (see figure 9-3 on page 9-6). 9.4.6.1 timer enable (te)?it 0 the timer enable (te) bit is used to enable or disable the timer. setting the te bit (te = 1) enables the timer and clears the timer count register (tcr). the counter starts counting according to the mode defined by tc[3:0]. clearing the te bit disables the timer. the te bit is cleared by hardware and software reset. note: when all the three timers are disabled and not in gpio mode, all three tio pins are tristated. in order to prevent undesired spikes on the tio pins (when switching from tri-state into active state), external pull-up or pull down resistors should be tied to the tio pins. 9.4.6.2 timer overflow interrupt enable (toie)?it 1 the timer overflow interrupt enable (toie) bit is used to enable the timer overflow interrupts. the overflow interrupt is generated after the counter wraparound occurs; that is, the counter value changes from $ffff to $0000 when a new event occurs. setting the toie bit enables the overflow interrupts. when the toie bit is cleared, the overflow interrupts are disabled. the toie bit is cleared by hardware and software reset. 9.4.6.3 timer compare interrupt enable (tcie)?it 2 the timer compare interrupt enable (tcie) bit is used to enable the timer compare interrupts. the compare interrupt is generated after the counter matches the compare register in the timer, pwm, or watchdog modes. if the tcpr is loaded with n, an interrupt occurs after (n ?m + 1) events, where m is tlr value. setting the tcie bit enables the compare interrupts. when the tcie bit is cleared, the compare interrupts are disabled. the tcie bit is cleared by hardware and software reset.
9-10 DSP56602 user? manual motorola triple timer module triple timer module programming model 9.4.6.4 timer control (tc[3:0])?its 4? the four timer control (tc[3:0]) bits control the source of the timer clock, the behavior of the tio pin and the timer mode of operation. table 9-2 summarizes the functionality of the tc bits. a detailed description of the timer operating modes is given in timer modes of operation on page 9-13. the tc[3:0] bits are cleared by hardware and software reset. to ensure proper functionality, the tc[3:0] bits should be changed only when the timer is disabled. note: if the clock is external, the counter is incremented by transitions on the tio pin. the external clock is internally synchronized to the internal clock and its frequency should be lower than the internal operating frequency divided by 4 (clk/4). table 9-2 tc[3:0] bit functionality tc3 tc2 tc1 tc0 tio clock mode 0000 gpio internal timer gpio 0001 output internal timer pulse 0010 output internal timer toggle 0011 input external event counter 0100 input internal input width 0101 input internal input period 0110 input internal capture 0111 output internal pulse width modulation(pwm) 1000 (reserved) 1001 output internal watchdog pulse 1010 output internal watchdog toggle 1011 (reserved) 1100 (reserved) 1101 (reserved) 1110 (reserved) 1111 output internal timer pulse
triple timer module triple timer module programming model motorola DSP56602 user? manual 9-11 9.4.6.5 inverter (inv)?it 8 the inverter (inv) bit affects the polarity of the external incoming signal on the tio pin when tio is programmed as input, and affects the polarity of the pulse generated on the tio pin when tio is programmed as output. in the timer modes, if the inv bit is set, the 1 to 0 transitions on the tio input pin increment the counter. if tio is programmed as input and the inv bit is cleared, the 0 to 1 transitions on the tio input pin increment the counter. in the input width mode, the inv bit determines whether the high pulse or the low pulse is measured. in the input period mode, the inv bit determines whether the period is measured between rising or falling edges. if tio is programmed as output and the inv bit is set, the pulse generated by the timer is inverted. if the inv bit is cleared, the pulse generated by the timer is of positive polarity. the inv bit is cleared by hardware and software reset. notes: 1. the inv bit affects both the timer and the gpio modes of operation. 2. to ensure proper functionality, the inv bit should be changed only when the timer is disabled or in gpio mode of operation. 3. when the tio is used as input to the prescaler, the polarity of the prescaler source clock is not affected by the corresponding inv bit. 9.4.6.6 timer reload mode (trm)?it 9 the timer reload mode (trm) control bit determines the counter preload operation. in timer and watchdog modes the counter is preloaded with the tlr value after the te bit is set and a first event occurs. if the trm bit is set, the counter is reloaded each time it reaches the value contained by the timer compare register and the new event occurs. in pwm mode, the counter is reloaded each time counter wraparound occurs (overflow) and the new event occurs. in measurement modes, the counter is preloaded with the tlr value (if trm = 1) on each appropriate edge of the input signal after the te bit is set. if trm is cleared, the counter operates as a free-running counter, incrementing on each incoming event. the trm bit is cleared by hardware and software reset. 9.4.6.7 direction (dir)?it 10 the direction (dir) control bit determines the behavior of the tio pin when used as a gpio pin. when the dir bit is set, the tio pin is an output. when the dir bit is cleared, the tio pin is an input.the tio pin can be used as a gpio pin only when tc0?c3 are all cleared. if one or more of tc0?c3 is not cleared, the gpio function is disabled and the dir bit has no effect. the dir bit is cleared by hardware and software reset. 9.4.6.8 data input (di)?it 11 the data input (di) bit reflects the value of tio pin according to the inv bit. reading the di bit reads the tio pin if inv = 0, or the inverted tio pin if inv = 1.
9-12 DSP56602 user? manual motorola triple timer module triple timer module programming model 9.4.6.9 data output (do)?it 12 the data output (do) bit writes data to the tio pin. when the gpio mode is enabled (tc0?c3 are all cleared) and dir = 1, the tio pin acts as data output. writing the do bit writes the data to the tio pin. if the inv bit is set, the data on the tio pin is inverted. when gpio mode is disabled, writing the do bit has no effect. the do bit is cleared by hardware and software reset. 9.4.6.10 timer overflow flag (tof)?it 13 the timer overflow flag (tof) bit, when set, indicates that counter wraparound has occurred. the timer overflow flag bit is cleared when writing a one into the tof bit. writing a 0 into the tof bit has no effect. the bit is also cleared when the timer overflow interrupt is serviced (timer overflow interrupt acknowledge). the tof bit is cleared by hardware and software reset, by the stop instruction, and by timer disabling (te = 0). 9.4.6.11 timer compare flag (tcf)?it 14 in the timer, pwm, and watchdog modes, the timer compare flag (tcf) bit when set indicates that (n ?m + 1) events are counted, where n is the value in the compare register and m is tlr value. in the measurement modes, the tcf bit when set indicates that the measurement has been completed. the timer compare flag bit is cleared when writing a 1 into the tcf bit. writing a 0 into the tcf bit has no effect. the bit is cleared also when the timer compare interrupt is serviced (timer compare interrupt acknowledge). the tcf bit is cleared by hardware and software reset, the stop instruction, and also by timer disabling (te = 0). notes: 1. writing a 0 in the tof or tcf bit can be done with the bit test and clear (bclr) instruction. the state of the tested bit is stored in the carry bit of the status register (sr). 2. tof and tcf are cleared by writing logic 1 to the specific bit. in order to assure that only the desired bit is cleared, the programmer should not use the bset command. the proper way to clear these bits is to write a logic 1 to the flag to be cleared and 0 to the other flag, using the movep instruction. 9.4.6.12 prescaled clock enable (pce)?it 15 the prescaled clock enable (pce) bit is used to select the prescaled clock as the timer source clock. when pce is cleared the timer uses either internal (clk/2) or external (tio) source clock as determined by the timer operating mode. when pce is set, the prescaler output is used as the timer source clock for the counter regardless of the timer operating mode. the pce bit is cleared by hardware and software reset.
triple timer module timer modes of operation motorola DSP56602 user? manual 9-13 notes: 1. to ensure proper functionality, the pce bit should be changed only when the timer is disabled. 2. the source clock for the prescaler is determined only by the prescaler source bits (ps0?s1) of the tplr. therefore, a timer can be clocked by prescaled clock derived from the tio of another timer. 9.4.6.13 reserved bit?it 3 bit 3 of the tcsr is reserved. it is read as 0 and should be written with 0 for future compatibility. 9.5 timer modes of operation the DSP56602 timers have the following four modes of operation: timer measurement pulse width modulation watchdog table 9-3 summarizes these modes, and the following paragraphs describe these modes in detail. table 9-3 timer mode summary mode mode description mode type tc[3:0] 0 timer mode, no output (internal clock) timer 0000 1 timer mode, output pulse enable (internal clock) timer 0001 2 timer mode, output toggle enable (internal clock) timer 0010 3 timer mode, output toggle enable (external clock) timer 0011 4 pulse width measurement mode measurement 0100 5 period measurement mode measurement 0101 6 capture mode measurement 0110 7 pulse width modulation mode, output toggle enable pwm 0111 8 (reserved) (reserved) 1000
9-14 DSP56602 user? manual motorola triple timer module timer modes of operation 9.5.1 timer modes timer modes allow using the timers to measure the duration of an event. 9.5.1.1 mode 0?imer, no output (internal clock) this mode is selected when tc[3:0] is set to 0000. in this mode, the counter is cleared after the te bit is set and loaded with the tlr value on the first timer pulse derived either from the dsp clock divided by two (clk/2) or from the prescaled clock input. the following timer pulses increment the counter. when the counter matches the value contained by the tcpr, the tcf bit in tcsr is set and, if the tcie is set, a compare interrupt is generated. at the next timer pulse, the counter is loaded with tlr value (if trm is set) and the count is resumed. if trm is cleared, the counter continues to be incremented on each timer pulse. if counter wraparound occurs, the tof bit is set, and if the toie is set, an overflow interrupt is generated. this process is repeated until the timer is disabled (the te bit is cleared). the counter contents can be read at any time by reading the tcr. 9.5.1.2 mode 1?imer, output pulse (internal clock) this mode is selected when tc[3:0] is set to 0001. in this mode, the counter is cleared after the te bit is set and loaded with the tlr value on the first timer pulse derived either from the dsp clock divided by two (clk/2) or from the prescaled clock input. the following timer pulses increment the counter. when the counter matches the value contained by the tcpr, the tcf bit in tcsr is set, and if the tcie is set, a compare interrupt is generated. at the next timer pulse, the counter is loaded with tlr value (if trm is set) and the count is resumed. if trm is cleared, the counter continues to be incremented on each timer pulse. this process is repeated until the timer is disabled 9 watchdog mode, output pulse enable (internal clock) watchdog 1001 10 watchdog mode, output toggle enable (internal clock) watchdog 1010 11 (reserved) (reserved) 1011 12 (reserved) (reserved) 1100 13 (reserved) (reserved) 1101 14 (reserved) (reserved) 1110 15 (reserved) (reserved) 1111 table 9-3 timer mode summary (continued) mode mode description mode type tc[3:0]
triple timer module timer modes of operation motorola DSP56602 user? manual 9-15 (te = 0). each time the counter matches the tcpr value, a pulse is output on the tio pin with the width equal to timer clock period. the pulse polarity is determined by the inv bit. if counter wraparound occurs, the tof bit is set, and if the toie is set, an overflow interrupt is generated. the counter contents can be read at any time by reading the tcr. note: after the te bit is set, the tio pin output value is set equal to the inv bit to guarantee the correct first pin transition. 9.5.1.3 mode 2?imer, output toggle (internal clock) this mode is selected when tc[3:0] is set to 0010. in this mode, the counter is cleared after the te bit is set and loaded with the tlr value on the first timer pulse derived either from the dsp clock divided by two (clk/2) or from the prescaled clock input. the following timer pulses increment the counter. when the counter matches the value of the tcpr, the tio output pin is toggled, the tcf bit in tcsr is set, and if the tcie bit is set, a compare interrupt is generated. at the next timer pulse, the counter is loaded with tlr value (if trm is set) and the count is resumed. if trm is cleared, the counter continues to be incremented on each timer pulse. this process is repeated until the timer is disabled (te = 0). the tio polarity is determined by the inv bit. on the first match, the tio output is set if the inv bit is cleared, or cleared if the inv bit is set. if counter wraparound occurs, the tof bit is set, and if the toie bit is set, an overflow interrupt is generated. the counter contents can be read at any time by reading the tcr. note: after the te bit is set, the tio pin output value is set equal to the inv bit to guarantee the correct first pin transition. 9.5.1.4 mode 3?imer, event counter (external clock) this mode is selected when tc[3:0] is set to 0011. in this mode, the counter is cleared after the te bit is set and loaded with the tlr value on the first transition on the source clock, which can be either the tio input pin or the prescaled clock input. the following transitions increment the counter. when the counter matches the value contained by tcpr, the tcf bit in the tcsr is set. if the tcie bit is set, a compare interrupt is generated. at the next transition, the counter is loaded with tlr value if the trm bit is set, and the count is resumed. if the trm bit is cleared, the counter continues to be incremented with each transition of the source clock. this process is repeated until the timer is disabled. the inv bit determines whether 0-to-1 transitions (the inv bit is cleared) or 1-to-0 transitions (the inv bit is set) increment the counter. if counter wraparound occurs, the tof bit is set, and if the toie bit is set, an overflow interrupt is generated. the counter contents can be read at any time by reading the tcr. the external clock is internally synchronized to the internal clock and its frequency should be lower than the dsp internal clock (clk) divided by four.
9-16 DSP56602 user? manual motorola triple timer module timer modes of operation 9.5.2 measurement modes since the measurement modes use the internal clock to increment the counter, but use the external signal for gating the count, synchronization is needed. the synchronization process can affect the measurement exactness by as much as a single selected internal or prescaled clock cycle. 9.5.2.1 mode 4?ulse width measurement the pulse width measurement mode is selected when tc[3:0] is set to 0100. in this mode, the counter is cleared after the te bit is set. after the first appropriate transition (as defined by the inv bit) occurring on the tio input pin, the counter is loaded with the tlr value on the first timer pulse derived either from the dsp internal clock (clk) divided by two or from the prescaled clock input. each subsequent timer pulse increments the counter. when the first edge of opposite polarity occurs on tio, the counter stops, the tcf bit in tcsr is set, and if the tcie bit is set, a compare interrupt is generated. the contents of the counter is loaded into the tcr and the user? program can read its value that represents the widths of the tio pulse. on the first timer pulse following the next transition that occurs on tio input pin, the counter is loaded with the value in tlr (if trm is set), and the count is resumed. if the trm bit is cleared, the counter continues to be incremented on each timer pulse. this process is repeated until the timer is disabled. if counter wraparound occurs, the tof bit is set. if the toie bit is set, an overflow interrupt is generated. in this mode, tio acts as a gating signal for the internal timer clock. the inv bit determines whether the counting is enabled when tio is low (the inv bit is set) or tio is high (the inv bit is cleared). 9.5.2.2 mode 5?eriod measurement the period measurement mode is selected when tc[3:0] is set to 0101. in this mode, the counter is cleared after the te bit is set. after the first appropriate transition (as defined by the inv bit) occurring on the tio input pin, it is loaded with the tlr value on the first timer pulse derived either from the dsp internal clock (clk) divided by two or from the prescaled clock input. each subsequent timer pulse increments the counter. on each following transition of the same polarity that occurs on tio, the tcf bit in the tcsr is set. if the tcie bit is set, a compare interrupt is generated. the contents of the counter is loaded in the tcr. the user? program can then read its value and the value in the tcr to determine the distance between tio edges. on the next timer pulse, the counter is loaded with the value in the tlr (if the trm bit is set) and the count is resumed. if the trm bit is cleared, the counter continues to be incremented on each timer pulse, accumulating measurements results. this process is repeated until the timer is disabled. if counter wraparound occurs, the tof bit is set. if the toie bit is set, an overflow interrupt is generated. the inv bit determines whether the period is measured
triple timer module timer modes of operation motorola DSP56602 user? manual 9-17 between consecutive 1 to 0 transitions of tio (the inv bit is set) or between consecutive 0 to 1 transitions of tio (the inv bit is cleared). 9.5.2.3 mode 6?apture the capture mode is selected when tc[3:0] is set to 0110. in this mode, the counter is cleared after the te bit is set and loaded with the tlr value on the first timer pulse derived either from the dsp clock divided by two (clk/2) or from the prescaled clock input. the following timer pulses increment the counter. if counter wraparound occurs, the tof bit is set, and if the toie is set, an overflow interrupt is generated. at the first transition of external clock, the tcf bit in tcsr is set, and if the tcie bit is set, a compare interrupt is generated. the contents of the counter are loaded into the tcr and the user? program can read the value that represents the delay of the leading detected edge in relation to the setting of the te bit. the counting is stopped. the inv bit determines whether the period is measured between the setting of te bit and the transitions of tio from 0 to 1 (the inv bit is cleared) or from 1 to 0 (the inv bit is set). 9.5.3 pulse width modulation mode one form of pulse width modulation (pwm) mode is provided, and is designated mode 7. 9.5.3.1 mode 7?wm, output toggle (internal clock) the pulse width modulation mode, output toggle enable mode, is selected when tc[3:0] is set to 0111. in this mode, the counter is cleared after the te bit is set and loaded with the tlr value on the first timer pulse derived either from the dsp clock divided by two (clk/2) or from the prescaled clock input. the following timer pulses increment the counter. when the counter matches the value of the tcpr, the tio output pin is toggled, the tcf bit in tcsr is set, and if the tcie bit is set, a compare interrupt is generated and the count is continued. when counter wraparound occurs, the tio output pin is toggled, the tof bit in tcsr is set, and if the toie is set, an overflow interrupt is generated. at the next timer pulse, the counter is loaded with tlr value (if the trm bit is set) and the count is resumed. if trm is cleared, the counter continues to be incremented on each timer pulse. this process is repeated until the timer is disabled. the tio polarity is determined by the inv bit. on the first transaction, the tio output is set if the inv bit is cleared, or cleared if the inv bit is set. the counter contents can be read at any time by reading the tcr. the value in tlr determines the output period ($ffff ?tlr + 1). the value in tcpr determines the duty cycle of the output signal ($ffff ?tcpr + 1 vs. $ffff ?tlr + 1). therefore, to ensure correct functionality, the values in tlr and tcpr should not be the same.
9-18 DSP56602 user? manual motorola triple timer module timer modes of operation note: after the timer is enabled, the tio pin output value is set equal to the inv bit to guarantee the correct first pin transition. 9.5.4 watchdog modes two watchdog modes are provided to ensure proper chip operation. 9.5.4.1 mode 9?atchdog, output pulse (internal clock) the watchdog mode, output pulse enable mode is selected when tc[3:0] is set to 1001. in this mode, the counter is cleared after the te bit is set and loaded with the tlr value on the first timer pulse derived either from the dsp clock divided by two (clk/2) or from the prescaled clock input. the following timer pulses increment the counter. when the counter matches the value of the tcpr, the tcf bit in tcsr is set, and if the tcie bit is set, a compare interrupt is generated and the count is continued. at the next timer pulse, the counter is loaded with tlr value (if trm is set) and the count is resumed. if the trm bit is cleared, the counter continues to be incremented on each timer pulse. this process is repeated until the timer is disabled. the counter is reloaded whenever the tlr is written with a new value while the timer is enabled. when counter wraparound occurs, the tof bit in the tcsr is set, and if the toie bit is set, an overflow interrupt is generated. at the same time, a pulse is output on the tio pin with the width equal to the timer clock period. the pulse polarity is determined by the inv bit. the counter contents can be read at any time by reading the tcr. note: in this mode, the internal hardware preserves the tio value and direction for an additional 2.5 internal clock cycles after reset was activated. this ensures a valid length reset when the tio is used as input to the reset pin. 9.5.4.2 mode 10?atchdog, output toggle (internal clock) the watchdog mode, output toggle enable mode is selected when tc[3:0] is set to 1010. in this mode, the counter is cleared after the te bit is set and loaded with the tlr value on the first timer pulse derived either from the dsp clock divided by two (clk/2) or from the prescaled clock input. the following timer pulses increment the counter. when the counter matches the value of the tcpr, the tcf bit in tcsr is set, and if the tcie bit is set, a compare interrupt is generated and the count is continued. at the next timer pulse, the counter is loaded with the tlr value (if the trm bit is set) and the count is resumed. if the trm bit is cleared, the counter continues to be incremented on each timer pulse. this process is repeated until the timer is disabled. the counter is reloaded whenever the tlr is written with a new value while the timer is enabled. when counter wraparound occurs, the tio output pin is toggled, the tof bit in the tcsr is set, and if the toie is set, an overflow interrupt is generated. the tio polarity is determined by the inv bit. on the first transaction, the tio output is set if the inv bit is cleared, or cleared if the inv bit is set. the counter contents can be read at any time by reading the tcr.
triple timer module timer modes of operation motorola DSP56602 user? manual 9-19 notes: 1. after the timer is enabled, the tio pin output value is set equal to inv bit to guarantee the correct first pin transition. 2. in this mode, the internal hardware preserves the tio value and direction for an additional 2.5 internal clock cycles after reset is activated, ensuring a valid length reset when the tio is used as input to the reset pin. 9.5.5 reserved modes timer modes 8, 11, 12, 13, 14 and 15 are reserved. 9.5.6 timer behavior during wait and stop instructions the timer clocks are active during the execution of the wait instruction. thus, timer activity continues undisturbed. on reaching the final event, if the timer interrupt is enabled, an interrupt is generated and the processor leaves the wait state and services the interrupt. the timer clocks are disabled during the execution of the stop instruction. thus, timer activity is stopped. in stop mode, the tio pins are electrically disconnected internally. if a tio pin is used as an input, changes that occur while in stop mode are ignored. to ensure proper operation, disable the timer before executing the stop instruction.
9-20 DSP56602 user? manual motorola triple timer module timer modes of operation
motorola DSP56602 user? manual 10-1 section 10 on-chip emulation module
10-2 DSP56602 user? manual motorola on-chip emulation module 10.1 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .10-3 10.2 once module pins. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .10-3 10.3 once controller. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .10-4 10.4 once memory breakpoint logic. . . . . . . . . . . . . . . . .10-10 10.5 once trace logic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .10-15 10.6 methods of entering the debug mode . . . . . . . . . .10-16 10.7 pipeline information and ogdbr . . . . . . . . . . . . . . . .10-18 10.8 trace buffer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .10-20 10.9 once commands and serial protocol . . . . . . . . . .10-23 10.10 target site debug system requirements . . . . . . .10-24 10.11 examples of using the once . . . . . . . . . . . . . . . . . . . .10-24 10.12 examples of jtag and once interaction . . . . . . . .10-29
on-chip emulation module introduction motorola DSP56602 user? manual 10-3 10.1 introduction the dsp56600 core on-chip emulation (once) module provides a means of interacting with the dsp56600 core and its peripherals non-intrusively so that a user can examine registers, memory, or on-chip peripherals, thus facilitating hardware and software development on the dsp56600 core processor. to achieve this, special circuits and dedicated pins on the DSP56602 are defined to avoid sacrificing any user-accessible on-chip resource. the once module resources can be accessed only after executing the jtag instruction enable_once (these resources are accessible even when the chip is operating in normal mode). see section 12, jtag port , for a description of the jtag functionality and its relation to the once. figure 10-1 shows the block diagram of the once module. 10.2 once module pins the once module controller functionality is accessed through the jtag test access port (tap). there are no dedicated once module pins for clock, data in, or data out. the jtag pins tck, tdi, and tdo are used to shift in and out data and instructions. see jtag pins on page 11-5 for the description of the jtag pins. to facilitate emulation-specific functions, one additional pin, called de , is provided on the DSP56602. figure 10-1 once module block diagram trace buffer breakpoint logic pipeline information trace logic once controller pab yab xab pdb pil gdb tdo trst tdi tck tags buffer control bus de aa0702
10-4 DSP56602 user? manual motorola on-chip emulation module once controller the bidirectional open drain debug event pin (de ) provides a fast means of entering the debug mode of operation from an external command controller (when input), as well as a fast means of acknowledging the entering of the debug mode of operation to an external command controller (when output). the assertion of this pin by a command controller causes the dsp56600 core to finish the current instruction being executed, save the instruction pipeline information, enter the debug mode, and wait for commands to be entered from the tdi line. if the de pin is used to enter the debug mode, then it must be deasserted after the once port responds with an acknowledge and before sending the first once command. the assertion of this pin by the dsp56600 core indicates that the dsp has entered the debug mode and is waiting for commands to be entered from the tdi line. the de pin also facilitates multiple processor connections, as shown in figure 10-2 . in this way, the user can stop all the devices in the system when one of the devices enters the debug mode. the user can also stop all the devices synchronously by asserting the de line. 10.3 once controller the once controller contains the following blocks: once command register (ocr), once decoder, and the status/control register. figure 10-3 illustrates a block diagram of the once controller. figure 10-2 once module multiprocessor configuration tdi tdo tdi tdo tdi tdo tdi tms tck de tdo trst aa0703 reset (optional)
on-chip emulation module once controller motorola DSP56602 user? manual 10-5 10.3.1 once command register (ocr) the once command register (ocr) is an 8-bit shift register that receives its serial data from the tdi pin. it holds the 8-bit commands to be used as input for the once decoder. the ocr is shown in figure 10-4 . 10.3.1.1 register select (rs[4:0])?its 0? the register select (rs[4:0]) bits define which register is source/destination for the read/write operation. table 10-1 shows the once register addresses. figure 10-3 once controller block diagram figure 10-4 once command register once command register tdi tck status and control register tdo mode select once decoder isdebug isbkpt isswdbg isdr istrace register write register read update aa0704 ocr once command register reset = $00 write only r/w go ex rs4 rs3 rs2 rs1 rs0 76543210 aa0106
10-6 DSP56602 user? manual motorola on-chip emulation module once controller table 10-1 once register select encoding rs[4:0] register selected 00000 once status and control register (oscr) 00001 once memory breakpoint counter (ombc) 00010 once breakpoint control register (obcr) 00011 (reserved) 00100 (reserved) 00101 memory limit register 0 (omlr0) 00110 memory limit register 1 (omlr1) 00111 (reserved) 01000 (reserved) 01001 once global data bus register (ogdbr) 01010 once program data bus register (opdbr) 01011 once pil register (opilr) 01100 once program data bus go-to register (for go to command) 01101 once trace counter (otc) 01110 (reserved) 01111 once pab register for fetch (opabfr) 10000 once pab register for decode (opabdr) 10001 once pab register for execute (opabex) 10010 trace buffer and increment pointer 10011 (reserved) 101xx (reserved) 11xx0 (reserved) 11x0x (reserved) 110xx (reserved) 11111 no register selected
on-chip emulation module once controller motorola DSP56602 user? manual 10-7 10.3.1.2 exit command (ex)?it 5 if the ex bit is set, leave debug mode and resume normal operation. the exit command is executed only if the go command is issued, and the operation is write to opdbr or read/write to ?o register selected? otherwise the ex bit is ignored. table 10-2 shows the definition of the ex bit. 10.3.1.3 go command (go)?it 6 if the go bit is set, execute the instruction that resides in the pil register. to execute the instruction, the core leaves the debug mode. the core returns to the debug mode immediately after executing the instruction if the ex bit is cleared. the core goes on to normal operation if the ex bit is set. the go command is executed only if the operation is write to opdbr or read/write to ?o register selected? otherwise, the go bit is ignored. table 10-3 shows the definition of the go bit. 10.3.1.4 read/write command (r/w )?it 7 the r/w bit specifies the direction of data transfer. table 10-4 shows the definition of the r/w bit. table 10-2 ex bit definition ex action 0 remain in debug mode 1 leave debug mode table 10-3 go bit definition go action 0 inactive?o action taken 1 execute instruction in pil table 10-4 r/w bit definition r/w action 0 write the data associated with the command into the register specified by rs[4:0]. 1 read the data contained in the register specified by rs[4:0].
10-8 DSP56602 user? manual motorola on-chip emulation module once controller 10.3.2 once decoder (odec) the once decoder (odec) supervises the entire once module activity. it receives as input the 8-bit command from the ocr, a signal from jtag controller (indicating that 8/24 bits have been received and update of the selected data register must be performed), and a signal indicating that the core was halted. the odec generates all the strobes required for reading and writing the selected once registers. 10.3.3 once status and control register (oscr) the once status and control register (oscr) is a 24-bit register used to enable the trace mode of operation and to indicate the cause of entering the debug mode. the control bits are read/write while the status bits are read-only. the oscr bits are cleared on hardware reset. the oscr is shown in figure 10-5 . 10.3.3.1 trace mode enable (tme)?it 0 when the trace mode enable (tme) control bit is set, the trace mode of operation is enabled. 10.3.3.2 interrupt mode enable (ime)?it 1 the interrupt mode enable (ime) control bit, when set, causes the chip to execute a vectored interrupt to the address vba:$06 instead of entering the debug mode. 10.3.3.3 software debug occurrence (swo)?it 2 the software debug occurrence (swo) bit is a read-only status bit that is set when the debug mode of operation is entered because of the execution of the debug or debugcc instruction with condition true. this bit is cleared when leaving the debug mode. figure 10-5 once status and control register (oscr) once status and control register read/write * * * * os1 os0 * to mbo swo ime tme * * * * 9876543210 23 * indicates reserved bits, written as 0 for future compatibility aa0705
on-chip emulation module once controller motorola DSP56602 user? manual 10-9 10.3.3.4 memory breakpoint occurrence (mbo)?it 3 the memory breakpoint occurrence (mbo) bit is a read-only status bit that is set when the debug mode of operation is entered because a memory breakpoint has been encountered. this bit is cleared when leaving the debug mode. 10.3.3.5 trace occurrence (to)?it 4 the trace occurrence (to) bit is a read-only status bit that is set when the debug mode of operation is entered when the trace counter is zero while trace mode is enabled. this bit is cleared when leaving the debug mode. 10.3.3.6 reserved bit?it 5 bit 5 of the oscr is reserved for future use. it is read as 0 and should be written with 0 for future compatibility. 10.3.3.7 core status (os[1:0])?its 6-7 the core status (os[1:0]) bits are read-only status bits that provide core status information. by examining the status bits, the user can determine whether the chip has entered the debug mode. examining swo, mbo, and to identifies the cause of entering the debug mode. the user can also examine these bits and determine the cause why the chip has not entered the debug mode after debug event assertion (de ) or as a result of the execution of the jtag debug_request instruction (core waiting for the bus, stop or wait instruction, etc.). these bits are also reflected in the jtag instruction shift register (ir), which allows the polling of the core status information at the jtag level. this is useful when the dsp56600 core executes the stop instruction (and therefore there are no clocks) to allow the reading of oscr. see table 10-5 for the definition of the os[1:0] bits. 10.3.3.8 reserved bits?its 8?3 bits 8?3 of the oscr are reserved for future use. they are read as 0 and should be written with 0 for future compatibility. table 10-5 core status bits description os[1:0] description 00 dsp56600 core is executing instructions 01 dsp56600 core is in wait or stop mode 10 dsp56600 core is waiting for bus 11 dsp56600 core is in debug mode
10-10 DSP56602 user? manual motorola on-chip emulation module once memory breakpoint logic 10.4 once memory breakpoint logic memory breakpoints can be set on program memory or data memory locations. in addition, the breakpoint does not have to be in a specific memory address, but within an approximate address range of where the program may be executing. this significantly increases the programmer? ability to monitor what the program is doing in real-time. the breakpoint logic, described in figure 10-6 , contains a latch for the addresses, registers that store the upper and lower address limit, address comparators, and a breakpoint counter. address comparators are useful in determining where a program may be getting lost or when data is being written where it should not be written. they are also useful in halting a program at a specific point to examine/change registers or memory. using address comparators to set breakpoints enables the user to set breakpoints in ram or rom and while in any operating mode. memory accesses are monitored according to the contents of the obcr as specified in once breakpoint control register (obcr) on page 10-12. figure 10-6 once memory breakpoint logic 0 memory address latch pab xab yab memory bus select memory limit register 1 address comparator 1 memory limit register 0 address comparator 0 tdi tdo tck breakpoint counter memory breakpoint selection dec breakpoint count = 0 occurred n,v n,v breakpoint control tdi tdo tck isbkpt aa0706
on-chip emulation module once memory breakpoint logic motorola DSP56602 user? manual 10-11 10.4.1 once memory address latch (omal) the once memory address latch (omal) is a 16-bit register that latches the pab, xab or yab on every instruction cycle according to the mbs1?bs0 bits in obcr. 10.4.2 once memory limit register 0 (omlr0) the once memory limit register 0 (omlr0) is a 16-bit register that stores the memory breakpoint limit.before enabling breakpoints, omlr0 must be loaded by the external command controller. omlr0 can be read or written through the tap. 10.4.3 once memory address comparator 0 (omac0) the once memory address comparator 0 (omac0) compares the current memory address (stored in omal0) with the omlr0 contents. 10.4.4 once memory limit register 1 (omlr1) the once memory limit register 1 (omlr1) is a 16-bit register that stores the memory breakpoint limit. omlr1 can be read or written through the tap. before enabling breakpoints, omlr1 must be loaded by the external command controller. 10.4.5 once memory address comparator 1 (omac1) the once memory address comparator 1 (omac1) compares the current memory address (stored in omal0) with the omlr1 contents.
10-12 DSP56602 user? manual motorola on-chip emulation module once memory breakpoint logic 10.4.6 once breakpoint control register (obcr) the once breakpoint control register (obcr) is a 16-bit register used to define the memory breakpoint events. obcr can be read or written through the jtag tap. all the bits of the obcr are cleared on hardware reset. the obcr is described in figure 10-7 . 10.4.6.1 memory breakpoint select bits (mbs[1:0])?its 0? the memory breakpoint select (mbs[1:0]) bits enable memory breakpoint0 and breakpoint1, allowing them to occur when a memory access is performed on p, x, or y space access is performed. see table 10-6 for the definition of the mbs[1:0] bits. 10.4.6.2 breakpoint0 read/write select (rw0[1:0])?its 2? the breakpoint 0 read/write select (rw0[1:0]) bits define the memory breakpoint0 to occur when a memory address accesses is performed for read, write or both. see table 10-7 for the definition of the rw0[1:0] bits. figure 10-7 once breakpoint control register (obcr) table 10-6 memory breakpoint select table mbs1 mbs0 description 0 0 reserved 0 1 breakpoint on p access 1 0 breakpoint on x access 1 1 breakpoint on y access once breakpoint control register reset = $0010 read/write bt1 bt0 cc cc rw rw cc cc rw rw mb mb * * * * 11109876543210 15 14 13 12 * indicates reserved bits, written as 0 for future compatibility 10 11 11 10 01 00 01 00 s1 s0 aa0707
on-chip emulation module once memory breakpoint logic motorola DSP56602 user? manual 10-13 10.4.6.3 breakpoint0 cc select (cc0[1:0])?its 4? the breakpoint0 condition code select (cc0[1:0]) bits define the condition of the comparison between the current memory address (omal0) and the memory limit register 0 (omlr0). see table 10-8 for the definition of the cc0[1:0] bits. 10.4.6.4 breakpoint1 read/write select (rw1[1:0])?its 6? the breakpoint1 read/write select (rw1[1:0]) bits control define memory breakpoints1 to occur when a memory address accesses is performed for read, write or both. see table 10-9 for the definition of the rw1[1:0] bits. table 10-7 breakpoint0 read/write select table rw01 rw00 description 0 0 breakpoint disabled 0 1 breakpoint on write access 1 0 breakpoint on read access 1 1 breakpoint on read or write access table 10-8 breakpoint0 condition select table cc01 cc00 description 0 0 breakpoint on not equal 0 1 breakpoint on equal 1 0 breakpoint on less than 1 1 breakpoint on greater than table 10-9 breakpoint1 read/write select table rw11 rw10 description 0 0 breakpoint disabled 0 1 breakpoint on write access 1 0 breakpoint on read access 1 1 breakpoint read or write access
10-14 DSP56602 user? manual motorola on-chip emulation module once memory breakpoint logic 10.4.6.5 breakpoint1 cc select (cc1[1:0])?its 8? the breakpoint1 condition code select (cc1[1:0]) bits define the condition of the comparison between the current memory address (omal0) and the once memory limit register 1 (omlr1). see table 10-10 for the definition of the cc1[1:0] bits. 10.4.6.6 breakpoint event select bits (bt[1:0])?its 10?1 the breakpoint event select (bt[1:0]) bits define the sequence between breakpoint0 and breakpoint1. if the condition defined by bt[1:0] is met, then the breakpoint counter (ombc) is decremented. see table 10-11 for the definition of the bt[1:0] bits. 10.4.6.7 reserved bits?its 12?5 bits 12?5 of the obcr are reserved for future use. they are read as 0 and should be written with 0 for future compatibility. 10.4.7 once memory breakpoint counter (ombc) the once memory breakpoint counter (ombc) is a 16-bit counter that is loaded with a value equal to the number of times minus one that a memory access event should occur before a memory breakpoint is declared. the memory access event is specified by the obcr and by the memory limit registers. on each occurrence of the memory access table 10-10 breakpoint1 condition select table cc11 cc10 description 0 0 breakpoint on not equal 0 1 breakpoint on equal 1 0 breakpoint on less than 1 1 breakpoint on greater than table 10-11 breakpoint0 and breakpoint1 event select table bt1 bt0 description 0 0 breakpoint0 and breakpoint1 0 1 breakpoint0 or breakpoint1 1 0 breakpoint1 after breakpoint0 1 1 breakpoint0 after breakpoint1
on-chip emulation module once trace logic motorola DSP56602 user? manual 10-15 event, the breakpoint counter is decremented. when the counter reaches 0 and a new occurrence takes place, the chip enters the debug mode. the ombc can be read or written through the tap. every time that the limit register is changed, or a different breakpoint event is selected in the obcr, the breakpoint counter must be written afterwards. this ensures that the once breakpoint logic is reset and that no previous events can affect the new breakpoint event selected. the breakpoint counter is cleared by hardware reset. 10.5 once trace logic using the once trace logic, execution of instructions in single or multiple steps is possible. the once trace logic causes the chip to enter the debug mode of operation after the execution of one or more instructions and wait for once commands from the debug serial port. the once trace logic block diagram is shown in figure 10-8 . the trace mode has a counter associated with it so that more than one instruction can be executed before returning back to the debug mode of operation. the objective of the counter is to allow the user to take multiple instruction steps real-time before entering the debug mode. this feature helps the software developer debug sections of code that do not have a normal flow or are getting hung up in infinite loops. the trace counter also enables the user to count the number of instructions executed in a code segment. the once trace counter (otc) is a 16-bit counter that can be read or written through the tap. if n instructions are to be executed before entering the debug mode, the trace counter should be loaded with n ?1. the trace counter is cleared by hardware reset. figure 10-8 once trace logic block diagram tdi tdo tck trace counter dec end of instruction count = 0 istrace aa0708
10-16 DSP56602 user? manual motorola on-chip emulation module methods of entering the debug mode to enable the trace mode of operation, do the following: 1. load the counter with a value. 2. set the program counter to the start location of the instruction(s) to be executed real-time. 3. set the tme bit in the oscr. 4. cause the dsp56600 core to exit the debug mode by executing the appropriate command issued by the external command controller. upon exiting the debug mode, the counter is decremented after each execution of an instruction. interrupts are serviceable and all instructions executed, including fast interrupt services and the execution of each repeated instruction, cause the trace counter to be decremented. upon decrementing to 0, the dsp56600 core re-enters the debug mode, the trace occurrence bit (to) in the oscr register is set, the core status bits os[1:0] are set to 11, and the de pin is asserted to indicate that the dsp56600 core has entered debug mode and is requesting service. 10.6 methods of entering the debug mode entering the debug mode is acknowledged by the chip by setting the os[1:0] bits and asserting the de line. this informs the external command controller that the chip has entered the debug mode and is waiting for commands.the dsp56600 core can disable the once module if the rom security option is implemented. if the rom security is implemented, the once module remains inactive until a write operation to the ogdbr is executed by the dsp56600 core. 10.6.1 external debug request during reset assertion holding the de line asserted during the assertion of reset causes the chip to enter the debug mode. after receiving the acknowledge, the external command controller must negate the de line before sending the first command. note: in this case, the chip does not execute any instruction before entering the debug mode.
on-chip emulation module methods of entering the debug mode motorola DSP56602 user? manual 10-17 10.6.2 external debug request during normal activity holding the de line asserted during normal chip activity causes the chip to finish the execution of the current instruction and then enter the debug mode. after receiving the acknowledge, the external command controller must negate the de line before sending the first command. this process is the same for any newly fetched instruction, including instructions fetched by the interrupt processing or instructions that will be aborted by the interrupt processing. note: in this case the chip completes the execution of the current instruction and stops after the newly fetched instruction enters the instruction latch. 10.6.3 executing the jtag debug_request instruction executing the jtag instruction debug_request asserts an internal debug request signal. consequently, the chip finishes the execution of the current instruction and stops after the newly fetched instruction enters the instruction latch. after entering the debug mode, the core status bits os1 and os0 are set and the de line is asserted, thus acknowledging the external command controller that the debug mode of operation has been entered. 10.6.4 external debug request during stop mode executing the jtag instruction debug_request (or asserting de ) while the chip is in the stop state (i. e., has executed a stop instruction) causes the chip to exit the stop state and enter the debug mode. after receiving the acknowledge, the external command controller must negate de before sending the first command. note: in this case, the chip completes the execution of the stop instruction and halts after the next instruction enters the instruction latch. 10.6.5 external debug request during wait mode executing the jtag instruction debug_request (or asserting de ) while the chip is in the wait state (i. e., has executed a wait instruction) causes the chip to exit the wait state and enter the debug mode. after receiving the acknowledge, the external command controller must negate de before sending the first command.
10-18 DSP56602 user? manual motorola on-chip emulation module pipeline information and ogdbr note: in this case, the chip completes the execution of the wait instruction and halts after the next instruction enters the instruction latch. 10.6.6 software request during normal activity upon executing the debug instruction (or debugcc when the specified condition is true), the chip enters the debug mode after the instruction following the debug instruction has entered the instruction latch. 10.6.7 enabling trace mode when the trace mode mechanism is enabled and the trace counter is greater than zero, the trace counter is decremented after each instruction execution. execution of an instruction when the value in the trace counter is 0 causes the chip to enter the debug mode after completing the execution of the instruction. only instructions actually executed cause the trace counter to decrement. an aborted instruction does not decrement the trace counter and does not cause the chip to enter the debug mode. 10.6.8 enabling memory breakpoints when the memory breakpoint mechanism is enabled with a breakpoint counter value of 0, the chip enters the debug mode after completing the execution of the instruction that caused the memory breakpoint to occur. in case of breakpoints on executed program memory fetches, the breakpoint is acknowledged immediately after the execution of the fetched instruction. in case of breakpoints on accesses to x, y, or p memory spaces by move instructions, the breakpoint is acknowledged after the completion of the instruction following the instruction that accessed the specified address. 10.7 pipeline information and ogdbr to restore the pipeline and to resume normal chip activity upon returning from the debug mode, a number of on-chip registers store the chip pipeline status. figure 10-9 shows the block diagram of the pipeline information registers, with the exception of the pab registers, which are shown in figure 10-10 on page 10-22.
on-chip emulation module pipeline information and ogdbr motorola DSP56602 user? manual 10-19 10.7.1 once pdb register (opdbr) the once program data bus register (opdbr) is a 24-bit latch that stores the value of the program data bus generated by the last program memory access of the core before the debug mode is entered. the opdbr register can be read or written through the tap. this register is affected by the operations performed during the debug mode and must be restored by the external command controller when returning to normal mode. 10.7.2 once pil register (opilr) the once pil register (opilr) is a 24-bit latch that stores the value of the instruction latch before the debug mode is entered. opilr can only be read through the tap. note: since the instruction latch is affected by the operations performed during the debug mode, it must be restored by the external command controller when returning to normal mode. since there is no direct write access to the instruction latch, the task of restoring is accomplished by writing to opdbr with no-go and no-ex. in this case, the data written on pdb is transferred into the instruction latch. figure 10-9 once pipeline information and gdb registers pdb register (opdbr) gdb register (ogdbr) tdi tdo tck pil register (opilr) pil pdb gdb aa0709
10-20 DSP56602 user? manual motorola on-chip emulation module trace buffer 10.7.3 once gdb register (ogdbr) the once gdb register (ogdbr) is a 16-bit latch that can only be read through the tap. the ogdbr is not actually required from a pipeline status restore point of view, but is required as a means of passing information between the chip and the external command controller. the ogdbr is mapped on the x internal i/o space at address $fffb. whenever the external command controller needs the contents of a register or memory location, it forces the chip to execute an instruction that brings that information to the ogdbr. then the contents of the ogdbr are delivered serially to the external command controller by the command ?ead gdb register? 10.8 trace buffer to ease debugging activity and keep track of program flow, the dsp56600 core provides a number of on-chip dedicated resources. there are three read-only pab registers that give pipeline information when the debug mode is entered, and a trace buffer that stores the address of the last instruction that was executed, as well as the addresses of the last eight change of flow instructions. 10.8.1 once pab register for fetch (opabfr) the once pab register for fetch register (opabfr) is a 16-bit register that stores the address of the last instruction whose fetch was started before the debug mode was entered.the opabfr can only be read through the tap. this register is not affected by the operations performed during the debug mode. 10.8.2 pab register for decode (opabdr) the once pab register for decode register (opabdr) is a 16-bit register that stores the address of the instruction currently on the pdb. this is the instruction whose fetch was completed before the chip has entered the debug mode. the opabdr can only be read through the tap. this register is not affected by the operations performed during the debug mode.
on-chip emulation module trace buffer motorola DSP56602 user? manual 10-21 10.8.3 once pab register for execute (opabex) the once pab register for execute (opabex) is a 16-bit register that stores the address of the instruction currently in the instruction latch. this is the instruction that would have been decoded and executed if the chip had not entered the debug mode. the opabex register can be read only through the tap. this register is not affected by the operations performed during the debug mode. 10.8.4 trace buffer the trace buffer stores the addresses of the last eight change of flow instructions that were executed, as well as the address of the last executed instruction. the trace buffer is implemented as a circular buffer containing eight 17-bit registers and one 4-bit counter. all the registers have the same address, but any read access to the trace buffer address causes the counter to increment, thus pointing to the next trace buffer register. the registers are serially available to the external command controller through their common trace buffer address. figure 10-10 shows the block diagram of the trace buffer. the trace buffer is not affected by the operations performed during the debug mode except for the trace buffer pointer increment when reading the trace buffer. when entering the debug mode, the trace buffer counter is pointing to the trace buffer register containing the address of the last executed instructions. the first trace buffer read obtains the oldest address and the following trace buffer reads get the other addresses from the oldest to the newest, in order of execution.
10-22 DSP56602 user? manual motorola on-chip emulation module trace buffer notes: 1. to ensure trace buffer coherence, a complete set of eight reads of the trace buffer must be performed. this is necessary because each read increments the trace buffer pointer, thus pointing to the next location. after eight reads, the pointer indicates the same location as before starting the read procedure. figure 10-10 once trace buffer fetch address (opabfr) pab decode address (opabdr) circular buffer pointer trace buffer shift register tdo tck trace buffer register 0 trace buffer register 1 trace buffer register 2 trace buffer register 7 execute address (opabex) tdi aa0710
on-chip emulation module once commands and serial protocol motorola DSP56602 user? manual 10-23 2. on any change of flow instruction, the trace buffer stores both the address of the change of flow instruction, as well as the address of the target of the change of flow instruction. in the case of conditional change of flows, the address of the change of flow instruction is always stored (regardless of the fact that the change of flow is true or false), but if the conditional change of flow is false (that is, not taken) the address of the target is not stored. in order to facilitate the program trace reconstruction every trace buffer location has an additional ?nvalid bit?(the 25th bit). if a conditional change of flow instruction has a ?ondition false? the ?nvalid bit?is set, thus marking this instruction as ?ot taken? therefore, it is imperative to read seventeen bits of data when reading the eight trace buffer registers. since data is read lsb first, the ?nvalid bit?is the first bit to be read. 10.9 once commands and serial protocol to permit an efficient means of communication between the external command controller and the DSP56602, the following protocol is adopted. before starting any debugging activity, the external command controller waits for an acknowledge on the de line indicating that the chip has entered the debug mode (optionally the external command controller can poll the os1 and os0 bits in the jtag instruction shift register). the external command controller communicates with the chip by sending 8-bit commands that can be accompanied by 24 bits of data. both commands and data are sent or received least significant bit first. after sending a command, the external command controller waits for the DSP56602 to acknowledge execution of the command. the external command controller sends a new command only after the chip has acknowledged execution of the previous command. the once commands are classified as follows: read commands (when the chip delivers the required data) write commands (when the chip receives data and writes the data in one of the once registers) commands that do not have data transfers associated with them the commands are 8 bits long and have the format shown in figure 10-4 on page 10-5.
10-24 DSP56602 user? manual motorola on-chip emulation module target site debug system requirements 10.10 target site debug system requirements a typical debug environment consists of a target system where the dsp56600 core-based device resides in the user defined hardware. the tap interfaces to the external command controller through a 14-pin connector that provides connections for the five jtag port lines, one once module control line, a ground, a reset line, and a target power input line. the reset line is optional and is only used to reset the dsp56600 core-based device and its associated circuitry. the external command controller acts as the medium between the dsp56600 core target system and a host computer. the external command controller circuit acts as a jtag tap driver and host computer command interpreter. the controller issues commands based on the host computer inputs from a user interface program that communicates with the user. 10.11 examples of using the once all the following examples of debugging procedures assume that the dsp is the only device in the jtag chain. if the chain has more than one device, the other devices can be forced to execute the jtag bypass instruction such that their effect in the serial stream will be one bit per additional device. the select-dr, select-ir, update-dr, and shift-dr events refer to bringing the jtag tap in the corresponding state. please refer to section 11, jtag , for a detailed description of the jtag protocol. 10.11.1 checking whether the chip has entered the debug mode there are two methods to verify that the chip has entered the debug mode: 1. every time the chip enters the debug mode, a pulse is generated on the de pin. a pulse is also generated every time the chip acknowledges the execution of an instruction while in debug mode. an external command controller can connect the de line to an interrupt pin in order to sense the acknowledge. 2. an external command controller can poll the jtag instruction shift register for the status bits os[1:0]. when the chip is in debug mode, these bits are set to the value 11. note: in the following paragraphs, ?ck?denotes the operation performed by the command controller to see if the debug mode has been entered, either by sensing de or by polling the jtag instruction shift register.
on-chip emulation module examples of using the once motorola DSP56602 user? manual 10-25 10.11.2 polling the jtag instruction shift register to poll the core status bits in the jtag instruction shift register, do the following: 1. select shift-ir. passing through capture-ir loads the core status bits into the instruction shift register. 2. shift in enable_once. while shifting in the new instruction, the captured status information is shifted out. pass through update-ir. 3. return to run-test/idle. the external command controller can analyze the information shifted out and detect whether the chip has entered the debug mode. note: jtag compliance requires a preamble of ?1?prior to shifting out status information. 10.11.3 saving pipeline information debugging is accomplished with dsp56600 core instructions supplied from the external command controller. therefore, the current state of the dsp56600 core pipeline must be saved prior to starting the debug activity, and the state must be restored prior to returning to the normal mode of operation. the following describes the saving procedure: 1. select shift-dr. shift in the ?ead pdb? pass through update-dr. 2. select shift-dr. shift out the 24-bit opdb register. pass through update-dr. 3. select shift-dr. shift in the ?ead pil? pass through update-dr. 4. select shift-dr. shift out the 24-bit opilr register. pass through update-dr. before starting the procedure, ensure that enable_once has been executed, and debug mode has been entered and verified, as described in checking whether the chip has entered the debug mode on page 10-24. there is no need to verify acknowledge between steps 1 and 2, as well as 3 and 4, because completion is guaranteed by design. 10.11.4 reading the trace buffer an optional step during debugging activity is reading the information associated with the trace buffer in order to enable an external program to reconstruct the full trace of the
10-26 DSP56602 user? manual motorola on-chip emulation module examples of using the once executed program. following is the description of the read trace buffer procedure (assume that all actions described in saving pipeline information have been executed): 1. select shift-dr. shift in the ?ead pabfr? pass through update-dr. 2. select shift-dr. shift out the 16-bit opabfr register. pass through update-dr. 3. select shift-dr. shift in the ?ead pabdr? pass through update-dr. 4. select shift-dr. shift out the 16 bit opabdr register. pass through update-dr. 5. select shift-dr. shift in the ?ead pabex? pass through update-dr. 6. select shift-dr. shift out the 16-bit opabex register. pass through update-dr. 7. select shift-dr. shift in the ?ead fifo? pass through update-dr. 8. select shift-dr. shift out the 17-bit fifo register. pass through update-dr. 9. repeat steps 7 and 8 for the entire fifo (8 times). note: the user must read the entire fifo, since each read increments the fifo pointer, thus pointing to the next fifo location. at the end of this procedure, the fifo pointer points back to the beginning of the fifo. the information that has been read by the external command controller now contains the address of the newly fetched instruction, the address of the instruction currently on the pdb, the address of the instruction currently on the instruction latch, as well as the addresses of the last eight instructions that have been executed and are change of flow. a user program can now reconstruct the flow of a full trace based on this information and on the original source code of the currently running program. 10.11.5 displaying a specified register the DSP56602 must be in debug mode and all actions described in saving pipeline information on page 10-25 have been executed. the sequence of actions is: 1. select shift-dr. shift in the ?rite pdb with go no-ex? pass through update-dr. 2. select shift-dr. shift in the 24-bit opcode: ?ove reg, x:ogdb? pass through update-dr to actually write opdbr and thus begin executing the move instruction. 3. wait for dsp to reenter debug mode (wait for de or poll core status). 4. select shift-dr and shift in ?ead gdb register? pass through update-dr (this selects ogdbr as the data register for read).
on-chip emulation module examples of using the once motorola DSP56602 user? manual 10-27 5. select shift-dr. shift out the ogdbr contents. pass through update-dr. wait for next command. 10.11.6 displaying x memory area starting at address $xxxx the DSP56602 must be in debug mode and all actions described in saving pipeline information on page 10-25 must have been executed. since r0 is used as pointer for the memory, r0 is saved first. the sequence of actions is: 1. select shift-dr. shift in the ?rite pdb with go no-ex? pass through update-dr. 2. select shift-dr. shift in the 24-bit opcode: ?ove r0, x:ogdb? pass through update-dr to actually write opdbr and begin executing the move instruction. 3. wait for dsp to reenter debug mode (wait for de or poll core status). 4. select shift-dr and shift in ?ead gdb register? pass through update-dr (this selects ogdbr as the data register for read). 5. select shift-dr. shift out the ogdbr contents. pass through update-dr. r0 is now saved. 6. select shift-dr. shift in the ?rite pdb with no-go no-ex? pass through update-dr. 7. select shift-dr. shift in the 24-bit opcode: ?ove #$xxxx,r0? pass through update-dr to actually write opdbr. 8. select shift-dr. shift in the ?rite pdb with go no-ex? pass through update-dr. 9. select shift-dr. shift in the second word of the 24-bit opcode: ?ove #$xxxx,r0? (the $xxxx field). pass through update-dr to actually write opdbr and execute the instruction. r0 is loaded with the base address of the memory block to be read. 10. wait for dsp to reenter debug mode (wait for de or poll core status). 11. select shift-dr. shift in the ?rite pdb with go no-ex? pass through update-dr. 12. select shift-dr. shift in the 24-bit opcode: ?ove x:(r0)+, x:ogdb? pass through update-dr to actually write opdbr and begin executing the move instruction. 13. wait for dsp to reenter debug mode (wait for de or poll core status).
10-28 DSP56602 user? manual motorola on-chip emulation module examples of using the once 14. select shift-dr and shift in ?ead gdb register? pass through update-dr (this selects ogdbr as the data register for read). 15. select shift-dr. shift out the ogdbr contents. pass through update-dr. the memory contents of address $xxxx is read. 16. select shift-dr. shift in the ?o select with go no-ex? pass through update-dr. this re-executes the same ?ove x:(r0)+, x:ogdb?instruction. 17. repeat from step 14 to complete the reading of the entire block. when finished, restore the original value of r0. note: polling for status through the jtag instruction register is preferable to reading the once status register through the dr path. 10.11.7 going from debug to normal mode in a current program in this case, the user has finished examining the current state of the machine, changed some of the registers, and wishes to return and continue execution of its program from the point where it stopped. therefore, the user must restore the pipeline of the machine end enable normal instruction execution. the sequence of actions is: 1. select shift-dr. shift in the ?rite pdb with no-go no-ex? pass through update-dr. 2. select shift-dr. shift in the 24 bits of saved pil (instruction latch value). pass through update-dr to actually write the instruction latch. 3. select shift-dr. shift in the ?rite pdb with go and ex? pass through update-dr. 4. select shift-dr. shift in the 24 bits of saved pdb. pass through update-dr to actually write the pdb. at the same time the internally saved value of the pab is driven back from the pabfr register onto the pab, the odec releases the chip from debug mode and the normal flow of execution is continued. 10.11.8 going from debug to normal mode in a new program in this case, the user has finished examining the current state of the machine, changed some of the registers, and wishes to start the execution of a new program (the goto command). therefore, the user must force a ?hange of flow?to the starting address of the new program ($xxxx). the sequence of actions is:
on-chip emulation module examples of jtag and once interaction motorola DSP56602 user? manual 10-29 1. select shift-dr. shift in the ?rite pdb with no-go no-ex? pass through update-dr. 1. select shift-dr. shift in the 24-bit ?0af080? which is the opcode of the jump instruction. pass through update-dr to actually write the instruction latch. 2. select shift-dr. shift in the ?rite pdb-go-to with go and ex? pass through update-dr. 3. select shift-dr. shift in the 16 bits of ?xxxx? pass through update-dr to actually write the pdb. at this time the odec releases the chip from debug mode and the execution is started from the address $xxxx. note: if the debug mode is entered during a do loop, rep instruction, or other special cases such as interrupt processing, stop, wait, or conditional branching, the user must first reset the DSP56602 before proceeding with the execution of the new program. 10.12 examples of jtag and once interaction this subsection lists the details of the jtag port/once module interaction and tms sequencing required to achieve the communication described in examples of using the once on page 10-24. the external command controller can force the DSP56602 into debug mode by executing the jtag instruction debug_request. in order to check that the DSP56602 has entered the debug mode, the external command controller must poll the status by reading the os[1:0] bits in the jtag instruction shift register. after executing the jtag instructions debug_request and enable_once and after the core status was polled to verify that the chip is in debug mode, the pipeline saving procedure must take place. the tms sequencing for this procedure is depicted in table 10-12 . the sequencing of enabling the once module is described in table 10-13 on page 10-30. table 10-12 tms sequencing for debug_request step tms jtag port once module note a 0 run-test/idle idle b 1 select-dr-scan idle c 1 select-ir-scan idle d 0 capture-ir idle the status is sampled in the shifter.
10-30 DSP56602 user? manual motorola on-chip emulation module examples of jtag and once interaction in ?tep n?the external command controller verifies that the os[1:0] bits have the value 11, indicating that the chip has entered the debug mode. if the chip has not yet entered the debug mode, the external command controller goes to ?tep b? ?tep c?etc. until the debug mode is acknowledged. e 0 shift-ir idle the four bits of the jtag debug_request (0111) are shifted in while status is shifted out. .................................................................. e 0 shift-ir idle f 1 exit1-ir idle g 1 update-ir idle the debug request is generated. h 1 select-dr-scan idle i 1 select-ir-scan idle j 0 capture-ir idle the status is sampled in the shifter. k 0 shift-ir idle the four bits of the jtag debug_request (0111) are shifted in while status is shifted out. .................................................................. k 0 shift-ir idle l 1 exit1-ir idle m 1 update-ir idle n 0 run-test/idle idle this step is repeated, enabling an external command controller to poll the status. ................................................ n 0 run-test/idle idle table 10-13 tms sequencing for enable_once step tms jtag port once module note a 1 test-logic-reset idle b 0 run-test/idle idle c 1 select-dr-scan idle d 1 select-ir-scan idle table 10-12 tms sequencing for debug_request (continued) step tms jtag port once module note
on-chip emulation module examples of jtag and once interaction motorola DSP56602 user? manual 10-31 e 0 capture-ir idle the core status bits are captured. f 0 shift-ir idle the four bits of the jtag enable_once instruction (0110) are shifted into the jtag instruction register while status is shifted out. g 0 shift-ir idle h 0 shift-ir idle i 0 shift-ir idle j 1 exit1-ir idle k 1 update-ir idle the once module is enabled. l 0 run-test/idle idle this step can be repeated, enabling an external command controller to poll the status. ................................................ l 0 run-test/idle idle table 10-14 tms sequencing for reading pipeline registers step tms jtag port once module note a 0 run-test/idle idle b 1 select-dr-scan idle c 0 capture-dr idle d 0 shift-dr idle the eight bits of the once command ?ead pil? (10001011) are shifted in. .................................................................. d 0 shift-dr idle e 1 exit1-dr idle f 1 update-dr execute ?ead pil the pil value is loaded in the shifter. g 1 select-dr-scan idle h 0 capture-dr idle table 10-13 tms sequencing for enable_once (continued) step tms jtag port once module note
10-32 DSP56602 user? manual motorola on-chip emulation module examples of jtag and once interaction during ?tep v?the external command controller stores the pipeline information and afterwards it can proceed with the debug activities as requested by the user. i 0 shift-dr idle the 24 bits of the pil are shifted out (24 steps). .................................................................. i 0 shift-dr idle j 1 exit1-dr idle k 1 update-dr idle l 1 select-dr-scan idle m 0 capture-dr idle n 0 shift-dr idle the eight bits of the once command ?ead pdb? (10001010) are shifted in. .................................................................. n 0 shift-dr idle o 1 exit1-dr idle p 1 update-dr execute ?ead pdb pdb value is loaded in shifter q 1 select-dr-scan idle r 0 capture-dr idle s 0 shift-dr idle the 24 bits of the pdb are shifted out (24 steps). .................................................................. s 0 shift-dr idle t 1 exit1-dr idle u 1 update-dr idle v 0 run-test/idle idle this step can be repeated, enabling an external command controller to analyze the information. ................................................ v 0 run-test/idle idle table 10-14 tms sequencing for reading pipeline registers (continued) step tms jtag port once module note
motorola DSP56602 user? manual 11-1 section 11 jtag port
11-2 DSP56602 user? manual motorola jtag port 11.1 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11-3 11.2 jtag pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11-5 11.3 tap controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11-6 11.4 dsp56600 restrictions . . . . . . . . . . . . . . . . . . . . . . . . . .11-12
jtag port introduction motorola DSP56602 user? manual 11-3 11.1 introduction the DSP56602 provides a dedicated user-accessible test access port (tap) that is fully compatible with the i eee 1149.1 standard test access port and boundary scan architecture . problems associated with testing high density circuit boards have led to development of this proposed standard under the sponsorship of the test technology committee of ieee and the joint test action group (jtag). the DSP56602 implementation supports circuit-board test strategies based on this standard. the test logic includes a tap that consists of five dedicated signal pins, a 16-state controller, and three test data registers. a boundary scan register (bsr) links all device signal pins into a single shift register. the test logic, implemented utilizing static logic design, is independent of the device system logic. the DSP56602 implementation provides the following capabilities: perform boundary scan operations to test circuit-board electrical continuity (extest). bypass the dsp56600 core for a given circuit-board test by effectively reducing the bsr to a single cell (bypass). sample the DSP56602 pins during operation and transparently shift out the result in the bsr. preload values to output pins prior to invoking the extest instruction (sample/preload). disable the output drive to pins during circuit-board testing (hi-z). provide a means of accessing the on-chip emulation (once) controller and circuits to control a target system (enable_once). provide a means of entering the debug mode of operation (debug_request). query identification information (manufacturer, part number and version) from the DSP56602 (idcode). force test data onto the outputs of a DSP56602 while replacing its boundary scan register in the serial data path with a single bit register (clamp). this section, which includes aspects of the jtag implementation that are specific to the DSP56602, is intended to be used with the supporting ieee 1149.1 document. the discussion includes those items required by the standard to be defined and, in certain cases, provides additional information specific to the DSP56602. for internal details and applications of the standard, refer to the ieee 1149.1 document. figure 11-1 shows a block diagram of the tap port.
11-4 DSP56602 user? manual motorola jtag port introduction figure 11-1 tap block diagram boundary scan register bypass mux 4-bit instruction register tdo tap ctrl tdi tms tck 0 2 3 1 once logic id register trst decoder mux aa0113
jtag port jtag pins motorola DSP56602 user? manual 11-5 11.2 jtag pins as described in the ieee 1149.1 document, the jtag port requires a minimum of four pins to support tdi, tdo, tck, and tms signals. the dsp56600 family also provides the optional trst pin. on the DSP56602, the debug event (de ) signal is provided for use by the once module, and is described in section 10, on-chip emulation module . the pin functions are described in the following paragraphs. 11.2.1 test clock (tck) the test clock input (tck) pin is used to synchronize the test logic. 11.2.2 test mode select (tms) the test mode select input (tms) pin is used to sequence the test controller? state machine. the tms is sampled on the rising edge of tck and it has an internal pullup resistor. 11.2.3 test data input (tdi) serial test instruction and data are received through the test data input (tdi) pin. tdi is sampled on the rising edge of tck and it has an internal pullup resistor. 11.2.4 test data output (tdo) the test data output (tdo) pin is the serial output for test instructions and data. tdo can be tri-stated and is actively driven in the shift-ir and shift-dr controller states. tdo changes on the falling edge of tck. 11.2.5 test reset (trst ) the test reset input (trst ) pin is used to asynchronously initialize the test controller. the trst pin has an internal pullup resistor.
11-6 DSP56602 user? manual motorola jtag port tap controller 11.3 tap controller the tap controller is responsible for interpreting the sequence of logical values on the tms signal. it is a synchronous state machine that controls the operation of the jtag logic. the state machine is shown in figure 11-2 . the tap controller responds to changes at the tms and tck signals. transitions from one state to another occur on the rising edge of tck. the value shown adjacent to each state transition represents the value of the tms signal sampled on the rising edge of tck signal. for a description of the tap controller states, please refer to i eee 1149.1 standard test access port and boundary scan architecture . figure 11-2 tap controller state machine select-dr-scan capture-dr shift-dr exit1-dr pause-dr exit2-dr test-logic-reset run-test/idle update-dr 1 0 0 1 0 1 1 0 1 1 0 0 1 0 select-ir-scan capture-ir shift-ir exit1-ir pause-ir exit2-ir update-ir 0 0 1 0 1 1 0 1 1 0 0 1 0 0 1 0 11 aa0114
jtag port tap controller motorola DSP56602 user? manual 11-7 11.3.1 boundary scan register the boundary scan register (bsr) in the DSP56602 jtag implementation contains bits for all device signal and clock pins and associated control signals. all DSP56602 bidirectional pins have a single register bit in the bsr for pin data, and are controlled by an associated control bit in the bsr. the DSP56602 bsr bit definitions are described in table 11-2 on page 11-13. 11.3.2 instruction register the DSP56602 jtag implementation includes the three mandatory public instructions (extest, sample/preload, and bypass), and also supports the optional clamp instruction defined by ieee 1149.1. the hi-z public instruction provides the capability for disabling all device output drivers. the enable_once public instruction enables the jtag port to communicate with the once circuitry. the debug_request public instruction enables the jtag port to force the dsp56600 core into the debug mode of operation. the dsp56600 core includes a 4-bit instruction register without parity consisting of a shift register with four parallel outputs. data is transferred from the shift register to the parallel outputs during the update-ir controller state. figure 11-3 shows the jtag instruction register. the four bits are used to decode the eight unique instructions shown in table 11-1 . all other encodings are reserved for future enhancements and are decoded as bypass. figure 11-3 jtag instruction register jtag instruction register (ir) b3 b2 b1 b0 aa0746
11-8 DSP56602 user? manual motorola jtag port tap controller the parallel output of the instruction register is reset to 0010 in the test-logic-reset controller state, which is equivalent to the idcode instruction. during the capture-ir controller state, the parallel inputs to the instruction shift register are loaded with 01 in the least significant bits as required by the standard. the two most significant bits are loaded with the values of the core status bits os1 and os0 from the once controller. see section 10, on-chip emulation module , for a description of the status bits. table 11-1 jtag instructions code instruction b3 b2 b1 b0 0000 extest 0001 sample/preload 0010 idcode 0011 clamp 0100 hi-z 0101 (reserved) 0110 enable_once 0111 debug_request 1 0 x x (reserved) 1 1 0 x (reserved) 1110 (reserved) 1111 bypass
jtag port tap controller motorola DSP56602 user? manual 11-9 11.3.2.1 extest (b[3:0] = 0000) the external test (extest) instruction selects the bsr. extest also asserts internal reset for the dsp56600 core system logic to force a predictable internal state while performing external boundary scan operations. by using the tap, the bsr is capable of the following: scanning user-defined values into the output buffers capturing values presented to input pins controlling the direction of bidirectional pins controlling the output drive of tri-stateable output pins for more details on the function and use of the extest instruction, please refer to the ieee 1149.1 document. 11.3.2.2 sample/preload (b[3:0] = 0001) the sample/preload instruction provides two separate functions. first, it provides a means to obtain a snapshot of system data and control signals. the snapshot occurs on the rising edge of tck in the capture-dr controller state. the data can be observed by shifting it transparently through the bsr. note: since there is no internal synchronization between the jtag clock (tck) and the system clock (clk), the user must provide some form of external synchronization to achieve meaningful results. the second function of the sample/preload instruction is to initialize the bsr output cells prior to selection of extest. this initialization ensures that known data appears on the outputs when entering the extest instruction. 11.3.2.3 idcode (b[3:0] = 0010) the idcode instruction selects the id register. this instruction is provided as a public instruction to allow the manufacturer, part number, and version of a component to be determined through the tap. figure 11-4 shows the id register configuration. for the DSP56602, the id number is $1182201d.
11-10 DSP56602 user? manual motorola jtag port tap controller one application of the id register is to distinguish the manufacturer(s) of components on a board when multiple sourcing is used. as more components emerge which conform to the ieee 1149.1 standard, it is desirable to allow for a system diagnostic controller unit to blindly interrogate a board design in order to determine the type of each component in each location. this information is also available for factory process monitoring and for failure mode analysis of assembled boards. motorola? manufacturer identity is 00000001110. the customer part number consists of two parts: motorola design center number (bits 27:22) and a sequence number (bits 21:12). the sequence number is divided into two parts: core number (bits 21:17) and chip derivative number (bits 16:12). motorola semiconductor israel (msil) design center number is 000110 and dsp56600 core number is 00001. for the DSP56602, the chip derivative number is 00010. once the idcode instruction is decoded, it selects the id register , which is a 32-bit data register. since the bypass register loads a logic 0 at the start of a scan cycle, whereas the id register loads a logic 1 into its least significant bit, examination of the first bit of data shifted out of a component during a test data scan sequence immediate following exit from test-logic-reset controller state shows whether such a register is included in the design. when the idcode instruction is selected, the operation of the test logic has no effect on the operation of the on-chip system logic as required by the ieee 1149.1 standard. 11.3.2.4 clamp (b[3:0] = 0011) the clamp instruction is not included in the ieee 1149.1 standard. it is provided as a public instruction that selects the 1-bit bypass register as the serial path between tdi and tdo while allowing signals driven from the component pins to be determined from the bsr. during testing of ics on pcb, it may be necessary to place static guarding values on signals that control operation of logic not involved in the test. the extest instruction could be used for this purpose, but since it selects the boundary scan figure 11-4 jtag id register 0 1 11 12 27 28 31 0 0 0 1 1 0 0 0 0 0 0 0 1 1 1 0 design core number chip derivative number 21 22 16 17 0 0 0 0 1 0 0 0 1 1 0 center number 0 0 0 1 0 manufacturer identity version information customer part number 1 aa1148
jtag port tap controller motorola DSP56602 user? manual 11-11 register the required guarding signals would be loaded as part of the complete serial data stream shifted in, both at the start of the test and each time a new test pattern is entered. since the clamp instruction allows guarding values to be applied using the boundary scan register of the appropriate ics while selecting their bypass registers, it allows much faster testing than does the extest instruction. data in the boundary scan cell remains unchanged until a new instruction is shifted in or the jtag state machine is set to its reset state. the clamp instruction also asserts internal reset for the dsp56600 core system logic to force a predictable internal state while performing external boundary scan operations. 11.3.2.5 hi-z (b[3:0] = 0100) the hi-z instruction is not included in the ieee 1149.1 standard. it is provided as a manufacturer? optional public instruction to prevent having to backdrive the output pins during circuit-board testing. when hi-z is invoked, all output drivers, including the two-state drivers, are turned off (i.e., high impedance). the instruction selects the bypass register. the hi-z instruction also asserts internal reset for the dsp56600 core system logic to force a predictable internal state while performing external boundary scan operations 11.3.2.6 enable_once(b[3:0] = 0110) the enable_once instruction is not included in the ieee 1149.1 standard. it is provided as a public instruction to allow the user to perform system debug functions. when the enable_once instruction is decoded the tdi and tdo pins are connected directly to the once registers. the particular once register connected between tdi and tdo at a given time is selected by the once controller depending on the once instruction being currently executed. all communication with the once controller is done through the select-dr-scan path of the jtag tap controller. see section 10, on-chip emulation module for more information. 11.3.2.7 debug_request(b[3:0] = 0111) the debug_request instruction is not included in the ieee 1149.1 standard. it is provided as a public instruction to allow the user to generate a debug request signal to the dsp56600 core. when the debug_request instruction is decoded, the tdi and tdo pins are connected to the instruction registers. due to the fact that in the capture-ir state of the tap the once status bits are captured in the instruction shift register, the external jtag controller must continue to shift in the debug_request instruction while polling the status bits that are shifted out until the debug mode of operation is entered (acknowledged by the combination 11 on os1?s0). after the acknowledgment of the debug mode is received, the external jtag controller must issue the enable_once instruction to allow the user to perform system debug functions.
11-12 DSP56602 user? manual motorola jtag port dsp56600 restrictions 11.3.2.8 bypass (b[3:0] = 1111) the bypass instruction selects the single-bit bypass register, as shown in figure 11-5 . this creates a shift register path from tdi to the bypass register, and finally to tdo, circumventing the bsr. this instruction is used to enhance test efficiency when a component other than the DSP56602 becomes the device under test. when the bypass register is selected by the current instruction, the shift-register stage is set to a logic 0 on the rising edge of tck in the capture-dr controller state. therefore, the first bit shifted out after selecting the bypass register is always a logic 0. 11.4 dsp56600 restrictions the control afforded by the output enable signals using the bsr and the extest instruction requires a compatible circuit-board test environment to avoid device-destructive configurations. the user must avoid situations in which the dsp56600 core output drivers are enabled into actively driven networks. in addition, the extest instruction can be performed only after power-up or regular hardware reset while extal was provided. then during the execution of extest, extal can remain inactive. there are two constraints related to the jtag interface. first, the tck input does not include an internal pullup resistor and should not be left unconnected. the second constraint is to ensure that the jtag test logic is kept transparent to the system logic by forcing the tap into the test-logic-reset controller state, using either of two methods. during power-up, trst must be externally asserted to force the tap controller into this state. after power-up is concluded, tms must be sampled as a logic 1 for five consecutive tck rising edges. if tms either remains unconnected or is connected to v cc , then the tap controller cannot leave the test-logic-reset state, regardless of the state of tck. the dsp56600 core features a low-power stop mode, which is invoked using the stop instruction. the interaction of the jtag interface with low-power stop mode is as follows: figure 11-5 bypass register 1 1 mux g1 c d to tdo from tdi 0 shift dr clockdr aa0115
jtag port dsp56600 restrictions motorola DSP56602 user? manual 11-13 1. the tap controller must be in the test-logic-reset state to either enter or remain in the low-power stop mode. leaving the tap controller test-logic-reset state negates the ability to achieve low-power, but does not otherwise affect device functionality. 2. the tck input is not blocked in low-power stop mode. to consume minimal power, the tck input should be externally connected to v cc or gnd. 3. the tms and tdi pins include on-chip pullup resistors. in low-power stop mode, these two pins should remain either unconnected or connected to v cc to achieve minimal power consumption. since during stop mode all DSP56602 clocks are disabled, the jtag interface provides the means of polling the device status (sampled in the capture-ir state). appendix c provides the boundary scan description language (bsdl) listing for the DSP56602. table 11-2 DSP56602 boundary scan register (bsr) bit definitions bit # cell type pin name pin type bsr cell type 0 bc_1 moda input data 1 bc_1 modb input data 2 bc_1 modc input data 3 bc_1 modd input data 4 bc_6 d23 input/output data 5 bc_6 d22 input/output data 6 bc_6 d21 input/output data 7 bc_6 d20 input/output data 8 bc_6 d19 input/output data 9 bc_6 d18 input/output data 10 bc_6 d17 input/output data 11 bc_6 d16 input/output data 12 bc_6 d15 input/output data 13 bc_1 d[23:12] control 14 bc_6 d14 input/output data 15 bc_6 d13 input/output data 16 bc_6 d12 input/output data
11-14 DSP56602 user? manual motorola jtag port dsp56600 restrictions 17 bc_6 d11 input/output data 18 bc_6 d10 input/output data 19 bc_6 d9 input/output data 20 bc_6 d8 input/output data 21 bc_6 d7 input/output data 22 bc_6 d6 input/output data 23 bc_6 d5 input/output data 24 bc_6 d4 input/output data 25 bc_6 d3 input/output data 26 bc_1 d[11:0] control 27 bc_6 d2 input/output data 28 bc_6 d1 input/output data 29 bc_6 d0 input/output data 30 bc_2 a15 output 2 data 31 bc_2 a14 output 2 data 32 bc_2 a13 output 2 data 33 bc_2 a12 output 2 data 34 bc_2 a11 output 2 data 35 bc_2 a10 output 2 data 36 bc_2 a9 output 2 data 37 bc_2 a8 output 2 data 38 bc_2 a7 output 2 data 39 bc_2 a6 output 2 data 40 bc_2 a5 output 2 data 41 bc_2 a4 output 2 data 42 bc_2 a3 output 2 data table 11-2 DSP56602 boundary scan register (bsr) bit definitions (continued) bit # cell type pin name pin type bsr cell type
jtag port dsp56600 restrictions motorola DSP56602 user? manual 11-15 43 bc_2 a2 output 2 data 44 bc_2 a1 output 2 data 45 bc_2 a0 output 2 data 46 bc_2 mcs output data 47 bc_2 rd output data 48 bc_2 wr output data 49 bc_2 at output data 50 bc_2 clkout output data 51 bc_1 extal input data 52 bc_1 reset input data 53 bc_1 had0 control 54 bc_6 had0 input/output data 55 bc_1 had1 control 56 bc_6 had1 input/output data 57 bc_1 had2 control 58 bc_6 had2 input/output data 59 bc_1 had3 control 60 bc_6 had3 input/output data 61 bc_1 had4 control 62 bc_6 had4 input/output data 63 bc_1 had5 control 64 bc_6 had5 input/output data 65 bc_1 had6 control 66 bc_6 had6 input/output data 67 bc_1 had7 control 68 bc_6 had7 input/output data table 11-2 DSP56602 boundary scan register (bsr) bit definitions (continued) bit # cell type pin name pin type bsr cell type
11-16 DSP56602 user? manual motorola jtag port dsp56600 restrictions 69 bc_1 has/a0 control 70 bc_6 has/a0 input/output data 71 bc_1 ha8/a1 control 72 bc_6 ha8/a1 input/output data 73 bc_1 ha9/a2 control 74 bc_6 ha9/a2 input/output data 75 bc_1 hcs/a10 control 76 bc_6 hcs/a10 input/output data 77 bc_1 tio0 control 78 bc_6 tio0 input/output data 79 bc_1 tio1 control 80 bc_6 tio1 input/output data 81 bc_1 tio2 ? control 82 bc_6 tio2 input/output data 83 bc_1 hreq/trq control 84 bc_6 hreq/trq input/output data 85 bc_1 hack/rrq control 86 bc_6 hack/rrq input/output data 87 bc_1 hrw/rd control 88 bc_6 hrw/rd input/output data 89 bc_1 hds/wr control 90 bc_6 hds/wr input/output data 91 bc_1 sck0 control 92 bc_6 sck0 input/output data 93 bc_1 sck1 control 94 bc_6 sck1 input/output data table 11-2 DSP56602 boundary scan register (bsr) bit definitions (continued) bit # cell type pin name pin type bsr cell type
jtag port dsp56600 restrictions motorola DSP56602 user? manual 11-17 95 bc_1 gpio2 control 96 bc_6 gpio2 input/output data 97 bc_1 gpio1 control 98 bc_6 gpio1 input/output data 99 bc_1 gpio0 control 100 bc_6 gpio0 input/output data 101 bc_1 sc00 control 102 bc_6 sc00 input/output data 103 bc_1 sc10 control 104 bc_6 sc10 input/output data 105 bc_1 std0 control 106 bc_6 std0 input/output data 107 bc_1 srd0 control 108 bc_6 srd0 input/output data 109 bc_1 pinit control 110 bc_6 pinit input/output data 111 bc_1 de control 112 bc_6 de input/output data 113 bc_1 sc01 control 114 bc_6 sc01 input/output data 115 bc_1 sc02 control 116 bc_6 sc02 input/output data 117 bc_1 std1 control 118 bc_6 std1 input/output data 119 bc_1 srd1 control 120 bc_6 srd1 input/output data table 11-2 DSP56602 boundary scan register (bsr) bit definitions (continued) bit # cell type pin name pin type bsr cell type
11-18 DSP56602 user? manual motorola jtag port dsp56600 restrictions 121 bc_1 sc11 control 122 bc_6 sc11 input/output data 123 bc_1 sc12 control table 11-2 DSP56602 boundary scan register (bsr) bit definitions (continued) bit # cell type pin name pin type bsr cell type
motorola DSP56602 user? manual a-1 appendix a bootstrap program 10 0 0 01 1 01 10 1000 011 01 1001 10 0 0 01 1 01 10 0100101001011010 101001010110110 1010101010010111 0101001010010111 1000101010100100 0100010101011101 1010100011010101 1001011001110100 10 0 0 01 1 01 10 0100101001011010 1010101010110110 1010101010010111 0101001010010111 1000101010100100 0100010101011101 1010100011010101 1001011001110100
a-2 DSP56602 user? manual motorola bootstrap program a.1 DSP56602 bootstrap listing . . . . . . . . . . . . . . . . . . . . . . a-3
bootstrap program motorola DSP56602 user? manual a-3 a.1 DSP56602 bootstrap listing the bootstrap source code listing provided in example a-1 is typical of the bootstrap code that can be created by the customer for programming the DSP56602. this listing is based on the bootstrap code found on the dsp56603. in conjunction with the dsp56603evm evaluation module or the dsp56603ads application development system, customers can use this listing to develop external rom programming for DSP56602 applications. notes: 1. this example for the DSP56602 does not take advantage of the functionality provided by the md bit. 2. when compiling source code, the correct x i/o equate and interrupt equate files (specified by ioequ.asm and intequ.asm) must be used. listings for these files are provided in appendix b, x i/o equates . example a-1 sample DSP56602 bootstrap listing ; sample bootstrap code for DSP56602 ; based on bootstrap code for dsp56603 - (c) copyright 1996, 1997 motorola inc. include "ioequ.asm" include "intequ.asm" ; written april 21, 1996 ; ; reset addresses: ; mode 0 $c000 (external) ; mode 8 $0000 (internal pram) ; mode 1-7 $1000 (internal prom) ; mode 9-f $1000 (internal prom) ; extern equ $8000 org p:$400 move omr,a and #<$7,a move #j_table,r0 move a,n0 move p:(r0+n0),r0 jmp (r0) j_table ; jump table starting address ; mode 0 dc error ; if mc:mb:ma=000, goto error (should reset to external) ; mode 1 (reserved mode) dc error ; if mc:mb:ma=001, goto error (reserved mode) ; mode 2 dc hostld68338 ; if mc:mb:ma=010, go load from 68338 (hi08)
a-4 DSP56602 user? manual motorola bootstrap program ; mode 3 dc eramlds ; if mc:mb:ma=011, go load from external slow (31 ws) ; 24 bit memory ; mode 4 dc epromlds ; if mc:mb:ma=100, go load from external slow (31 ws) ; 8 bit memory ; mode 5 dc isahostld ; if mc:mb:ma=101, go load from isa (hi08) ; mode 6 dc hc11hostld ; if mc:mb:ma=110, go load from hc11 (hi08) ; mode 7 dc typ2 ; if mc:mb:ma=111, go to typ2 current consumption test ;=============================================================================== ; this routine loads a program through the hi08 host port ; the program is downloaded from the host mcu with the following rules: ; 1) 2 bytes - define the program length. ; 2) 2 bytes - define the address to which to start loading the program to. ; 3) 2 bytes - define the address to jump to after program is loaded ; 4) 4n bytes (while n is any integer number) ; the program words will be stored in contiguous pram memory locations starting ; at the specified starting address. ; after reading the program words, program execution starts from the same address ; where loading started. ; the host mcu may terminate the loading process by setting the hf1=0 and hf0=1. ; when the downloading is terminated, the program will start execution of the ; loaded program ; from the specified starting address. ; the hi08 boot rom program enables the following busses to download programs ; through the hi08 port: ; ; 1 - isa ; 2 - hc11 ; 3 - 68338 ;======================================================================================= hostld68338 ; boot from 68338 host processor movep #%0000000100110000,x:m_hpcr; configure the following conditions: ; hap = 0 negative host acknowledge ; hrp = 0 negative host request ; hcsp = 0 negative chip select input ; hd/hs = 0 single strobe bus (r/w~ and ds strobes) ; hmux = 0 non multiplexed bus ; hasp = 0 (address strobe polarity has no ; meaning in non-multiplexed bus) ; hdsp = 0 negative data strobes polarity ; hrod = 1 host request is open-drain ; spare = 0 set this bit to 0 for future compatibility ; hen = 0 when the hpcr register is ; modified hen should be cleared example a-1 sample DSP56602 bootstrap listing (continued)
bootstrap program motorola DSP56602 user? manual a-5 ; haen = 1 host acknowledge is enabled ; hren = 1 host requests are enabled ; hcsen = 0 host chip select input disabled ; ha9en = 0 (address 9 enable bit has no meaning in ; non-multiplexed bus) ; ha8en = 0 (address 8 enable bit has no meaning in ; non-multiplexed bus) ; hgen = 0 host gpio pins are disabled jmp hi08con isahostld ; boot from isa bus movep #%0101000000011000,x:m_hpcr ; configure the following conditions: ; hap = 0 negative host acknowledge ; hrp = 1 positive host request ; hcsp = 0 negative chip select input ; hd/hs = 1 dual strobes bus (rd and wr strobes) ; hmux = 0 non multiplexed bus ; hasp = 0 (address strobe polarity has no meaning in ; non-multiplexed bus) ; hdsp = 0 negative data strobes polarity ; hrod = 0 host request is active when enabled ; spare = 0 set this to 0 for future compatibility ; hen = 0 clear hen when the hpcr register is modified ; haen = 0 host acknowledge is disabled ; hren = 1 host requests are enabled ; hcsen = 1 host chip select input enabled ; ha9en = 0 (address 9 enable bit has no meaning in ; non-multiplexed bus) ; ha8en = 0 (address 8 enable bit has no meaning in ; non-multiplexed bus) ; hgen = 0 host gpio pins are disabled jmp hi08cont hc11hostld ; boot from 68hc11 processor movep #%0000001000011000,x:m_hpcr ; configure the following conditions: ; hap = 0 negative host acknowledge ; hrp = 0 negative host request ; hcsp = 0 negative chip select input ; hd/hs = 0 single strobe bus (r/w~ and ds strobes) ; hmux = 0 non multiplexed bus ; hasp = 0 (address strobe polarity has no meaning in ; non-multiplexed bus) ; hdsp = 1 negative data strobes polarity ; hrod = 0 host request is active when enabled ; spare = 0 set this bit to 0 for future compatibility ; hen = 0 clear hen when the hpcr register is modified ; haen = 0 host acknowledge is disabled example a-1 sample DSP56602 bootstrap listing (continued)
a-6 DSP56602 user? manual motorola bootstrap program ; hren = 1 host requests are enabled ; hcsen = 1 host chip select input enabled ; ha9en = 0 (address 9 enable bit has no meaning in ; non-multiplexed bus) ; ha8en = 0 (address 8 enable bit has no meaning in ; non-multiplexed bus) ; hgen = 0 host gpio pins are disabled hi08cont bset #m_hen,x:m_hpcr ; enable hi08 to operate as host interface (set hen=1) jclr #m_hrdf,x:m_hsr,* ; wait for the program length to be written movep x:m_hrx,a0 ; download length in a0 jclr #m_hrdf,x:m_hsr,* ; wait for the program starting address to be written movep x:m_hrx,r0 ; destination starting address in r0 jclr #m_hrdf,x:m_hsr,* ; wait for the program address to jump to ; after program is loaded movep x:m_hrx,r1 ; target branch address in r1 nop do a0,hi08loop ; set a loop with the downloaded length counts hi08ll jset #m_hrdf,x:m_hsr,hi08nw ; if new word was loaded then jump to read that word jclr #m_hf0,x:m_hsr,hi08ll ; if hf0=0 then continue with the downloading enddo ; must terminate the do loop jmp hi08loop hi08nw movep x:m_hrx,x:m_bpmrl ; low 16 bits of the 24-bit program word hi08ll1 jset #m_hrdf,x:m_hsr,hi08nw1 ; if new word was loaded then jump to read that word jclr #m_hf0,x:m_hsr,hi08ll1 ; if hf0=0 then continue with the downloading enddo ; must terminate the do loop jmp hi08loop hi08nw1 movep x:m_hrx,x:m_bpmrh ; high 8 bits of the 24-bit program word movep x:m_bpmrg,p:(r0)+ ; move the new word into its destination location ; in the program ram example a-1 sample DSP56602 bootstrap listing (continued)
bootstrap program motorola DSP56602 user? manual a-7 nop nop nop hi08loop jmp finish ;======================================================================== ; this routine loads from external slow (31 ws) 24 bit memory. eramlds move#extern,r2 ; r2 = address of external eprom movem p:(r2)+,r0 ; read starting address to load to r0 movem p:(r2)+,r7 ; read number of words to load to r7 movem p:(r2)+,r1 ; read starting address to jump to after loading, into r1 do r7,eramldsloop ; read program words movepp:(r2)+,x:m_bpmrg ; get 24 bit word from ext. p mem. movepx:m_bpmrg,p:(r0)+ ; store 24-bit word in p ram. nop nop nop eramldsloop ; and go get another 24-bit word. jmp finish ; boot from eprom done ;======================================================================= ; this routine loads from external slow (31 ws) 8 bit eprom. epromlds move #extern,r2 ; r2 = address of external eprom do #4,_loop8 ; read number of words and starting address to load to movem p:(r2)+,a2 ; get the 8 lsb from ext. p mem. asr #8,a,a ; shift 8 bit data into a1 nop nop _loop8 ; nop move a1,r0 ; starting address for load move a0,r7 ; a0 holds the number of words do #2,_loop9 ; read starting address to jump to after loading movem p:(r2)+,a2 ; get the 8 lsb from ext. p mem. asr #8,a,a ; shift 8 bit data into a1 nop nop loop9 ; nop move a1,r1 ; save it in r1 nop move a1,r1 ; save it in r1 example a-1 sample DSP56602 bootstrap listing (continued)
a-8 DSP56602 user? manual motorola bootstrap program _do r7,_loop10 ; read program words do #2,_loop11 ; get lower 16 bits of each 24-bit instruction movem p:(r2)+,a2 ; get the 8 lsb from ext. p mem. asr #8,a,a ; shift 8 bit data into a1 nop nop _loop11 ; go get another byte. movep a1,x:m_bpmrl ; store 16-bit result in bpmrl movem p:(r2)+,a1 ; get the 8 lsb from ext. p mem. movep a1,x:m_bpmrh ; store 16-bit result in bpmrl movep x:m_bpmrg,p:(r0)+ ; store 24-bit result in p mem. nop nop _loop10 ; and go get another 24-bit word. ; boot from eprom done ;======================================================================== finish ; this is the exit handler that returns execution to normal ; expanded mode and jumps to the reset vector. andi #$0,ccr ; clear ccr as if reset to 0. jmp (r1) ; then go to starting prog address. typ2 move #px,r0 move #0,r1 do #64,pxe ; copy x data to xram move p:(r0)+,x0 move x0,x:(r1)+ nop nop pxe move #py,r0 move #0,r1 do #64,pye ; copy y data to y ram move p:(r0)+,x0 move x0,y:(r1)+ nop nop pye bset #7,x:m_pctl1 ; clkout disable bset #4,x:m_pctl1 ; xtal disable ori #$10,omr ;set edb ori #$20,omr ;set pcd example a-1 sample DSP56602 bootstrap listing (continued)
bootstrap program motorola DSP56602 user? manual a-9 move #$0,r0 move #$0,r4 move #$3f,m0 move #$3f,m4 clr a clr b move #$0,x0 move #$0,x1 move #$0,y0 move #$0,y1 loop do forever,_end mac x0,y0,a x:(r0)+,x1 y:(r4)+,y1 mac x1,y1,a x:(r0)+,x0 y:(r4)+,y0 add a,b mac x0,y0,a x:(r0)+,x1 mac x1,y1,a y:(r4)+,y0 move b1,x:$ff _end px dc $2eb9 dc $f2fe dc $6a5f dc $6cac dc $fd75 dc $10a dc $6d7b dc $a798 dc $fbf1 dc $63d6 dc $6657 dc $a544 dc $662d dc $e762 dc $f0f3 dc $f1b0 dc $829 dc $f7ae dc $a94f dc $78dc dc $2de5 dc $e0ba dc $ab6b dc $26c8 dc $361 dc $6e86 dc $7347 dc $e774 example a-1 sample DSP56602 bootstrap listing (continued)
a-10 DSP56602 user? manual motorola bootstrap program dc $349d dc $ed12 dc $fce3 dc $26e0 dc $7d99 dc $a85e dc $a43f dc $b10c dc $a55 dc $ec6a dc $255b dc $f1f8 dc $26d1 dc $6536 dc $bc37 dc $35a4 dc $f0d dc $bec2 dc $e4d3 dc $e810 dc $f09 dc $e50e dc $fb2f dc $753c dc $62c5 dc $641a dc $3b4b dc $a928 dc $6641 dc $a7e6 dc $2127 dc $2fd4 dc $57d dc $3c72 dc $8c3 dc $7540 py dc $6da dc $f70b dc $39e8 dc $e801 dc $66a6 dc $f8e7 dc $ec94 dc $233d dc $2732 dc $3c83 dc $3e00 dc $b639 example a-1 sample DSP56602 bootstrap listing (continued)
bootstrap program motorola DSP56602 user? manual a-11 dc $a47e dc $fddf dc $a2c dc $7cf5 dc $6a8a dc $b8fb dc $ed18 dc $f371 dc $a556 dc $e9d7 dc $a2c4 dc $35ad dc $e0e2 dc $2c73 dc $2730 dc $7fa9 dc $292e dc $3ccf dc $a65c dc $6d65 dc $a3a dc $b6eb dc $ac48 dc $7ae1 dc $3006 dc $f6c7 dc $64f4 dc $e41d dc $2692 dc $3863 dc $bc60 dc $a519 dc $39de dc $f7bf dc $3e8c dc $79d5 dc $f5ea dc $30db dc $b778 dc $fe51 dc $a6b6 dc $ffb7 dc $f324 dc $2e8d dc $7842 dc $e053 dc $fd90 dc $2689 dc $b68e example a-1 sample DSP56602 bootstrap listing (continued)
a-12 DSP56602 user? manual motorola bootstrap program dc $2eaf dc $62bc dc $a245 error bset #7,x:m_pctl1 ; clockout disable bset #4,x:m_pctl1 ; xtal disable bclr #6,x:m_pctl1 ; pll disable ori #$10,omr ;set edb ori #$20,omr ;set pcd nop nop nop nop nop stop nop nop nop example a-1 sample DSP56602 bootstrap listing (continued)
motorola DSP56602 user? manual b-1 appendix b x i/o equates 10 0 0 01 1 01 10 1000 011 01 1001 10 0 0 01 1 01 10 0100101001011010 101001010110110 1010101010010111 0101001010010111 1000101010100100 0100010101011101 1010100011010101 1001011001110100 10 0 0 01 1 01 10 0100101001011010 1010101010110110 1010101010010111 0101001010010111 1000101010100100 0100010101011101 1010100011010101 1001011001110100
b-2 DSP56602 user? manual motorola x i/o equates b.1 DSP56602 x i/o equates . . . . . . . . . . . . . . . . . . . . . . . . . . . b-3 b.2 DSP56602 interrupt equates . . . . . . . . . . . . . . . . . . . . b-10
x i/o equates motorola DSP56602 user? manual b-3 b.1 DSP56602 x i/o equates example b-1 provides x i/o equates for the DSP56602. if bootstrap code is developed for the DSP56602 (for external bootstrap loading), this listing should be enclosed in a file titled ioequ.asm for inclusion in the bootstrap executable. example b-1 DSP56602 x i/o equates ;***************************************************************************** ; ; equates for DSP56602 i/o registers and ports ; reference: DSP56602 specifications revision 2.00 ; ; 1st update: june 6 1995 (creation, ; copied from dsp56301 and modified) by zvika r. ; ; last update: nov. 21 1995 (verified with verilog model, ; corrected m_ps from $6000 to $c000, ; changed to DSP56602 from dsp56601, ; added new pd pll bits) by zvika r. ; ;***************************************************************************** page 132,55,0,0,0 opt mex DSP56602 equ 1 ioequ ident 1,0 ;------------------------------------------------------------------------ ; equates for i/o port programming ;------------------------------------------------------------------------ ; register addresses m_hddr equ $ffc8 ; host port gpio data direction register m_hdr equ $ffc9 ; host port gpio data register m_pcrc equ $ffbf ; ssi0 port control register m_prrc equ $ffbe ; ssi0 gpio direction register m_pdrc equ $ffbd ; ssi0 gpio data register m_pcrd equ $ffaf ; ssi1 port control register m_prrd equ $ffae ; ssi1 gpio direction data register m_pdrd equ $ffad ; ssi1 gpio data register m_pcre equ $ff9f ; gpio control register m_prre equ $ff9e ; gpio direction register m_pdre equ $ff9d ; gpio data register m_ogdb equ $fffb ; once gdb register
b-4 DSP56602 user? manual motorola x i/o equates ;------------------------------------------------------------------------ ; equates for host interface ;------------------------------------------------------------------------ ; register addresses m_hcr equ $ffc2 ; host control register m_hsr equ $ffc3 ; host status rgister m_hpcr equ $ffc4 ; host polarity control register m_hbar equ $ffc5 ; host base address register m_hrx equ $ffc6 ; host recceive register m_htx equ $ffc7 ; host transmit register ; hcr bits definition m_hrie equ $0 ; host receive interrupts enable m_htie equ $1 ; host transmit interrupt enable m_hcie equ $2 ; host command interrupt enable m_hf2 equ $3 ; host flag 2 m_hf3 equ $4 ; host flag 3 ; hsr bits definition m_hrdf equ $0 ; host receive data full m_htde equ $1 ; host receive data emptiy m_hcp equ $2 ; host command pending m_hf0 equ $3 ; host flag 0 m_hf1 equ $4 ; host flag 1 ; hpcr bits definition m_hgen equ $0 ; host port gpio enable m_ha8en equ $1 ; host address 8 enable m_ha9en equ $2 ; host address 9 enable m_hcsen equ $3 ; host chip select enable m_hren equ $4 ; host request enable m_haen equ $5 ; host acknowledge enable m_hen equ $6 ; host enable m_hod equ $8 ; host request open drain mode m_hdsp equ $9 ; host data strobe polarity m_hasp equ $a ; host address strobe polarity m_hmux equ $b ; host multiplexed bus select m_hd_hs equ $c ; host double/single strobe select m_hcsp equ $d ; host chip select polarity m_hrp equ $e ; host request polaritypolarity m_hap equ $f ; host acknowledge polarity example b-1 DSP56602 x i/o equates (continued)
x i/o equates motorola DSP56602 user? manual b-5 ;------------------------------------------------------------------------ ; equates for synchronous serial interface (ssi) ;------------------------------------------------------------------------ ; register addresses of ssi0 m_tx0 equ $ffbc ; ssi0 transmit data register m_tsr0 equ $ffbb ; ssi0 time slot register m_rx0 equ $ffba ; ssi0 receive data register m_ssisr0 equ $ffb9 ; ssi0 status register m_crc0 equ $ffb8 ; ssi0 control register c m_crb0 equ $ffb7 ; ssi0 control register b m_cra0 equ $ffb6 ; ssi0 control register a ; register addresses of ssi1 m_tx1 equ $ffac ; ssi1 transmit data register 0 m_tsr1 equ $ffab ; ssi1 time slot register m_rx1 equ $ffaa ; ssi1 receive data register m_ssisr1 equ $ffa9 ; ssi1 status register m_crc1 equ $ffa8 ; ssi1 control register c m_crb1 equ $ffa7 ; ssi1 control register b m_cra1 equ $ffa6 ; ssi1 control register a ; ssi control register a bit flags m_psr equ 15 ; prescaler range m_dc equ $1f00 ; frame rate divider control mask (dc0-dc7) m_wl equ $6000 ; word length control mask (wl0-wl7) ; ssi control register b bit flags m_of equ $3 ; serial output flag mask m_of0 equ 0 ; serial output flag 0 m_of1 equ 1 ; serial output flag 1 m_sste equ 8 ; ssi transmit enable m_ssre equ 9 ; ssi receive enable m_sstie equ 10 ; ssi transmit interrupt enable m_ssrie equ 11 ; ssi receive interrupt enable m_stlie equ 12 ; ssi transmit last slot interrupt enable m_srlie equ 13 ; ssi receive last slot interrupt enable m_steie equ 14 ; ssi transmit error interrupt enable m_sreie equ 15 ; ssi receive error interrupt enable example b-1 DSP56602 x i/o equates (continued)
b-6 DSP56602 user? manual motorola x i/o equates ; ssi control register c bit flags m_syn equ 0 ; sync/async control m_mod equ 1 ; ssi mode select m_scd equ $1c ; serial control direction mask m_scd0 equ 2 ; serial control 0 direction m_scd1 equ 3 ; serial control 1 direction m_scd2 equ 4 ; serial control 2 direction m_sckd equ 5 ; clock source direction m_ckp equ 6 ; clock polarity m_shfd equ 7 ; shift direction m_fsl equ $3000 ; frame sync length mask (fsl0-fsl1) m_fsl0 equ 12 ; frame sync length 0 m_fsl1 equ 13 ; frame sync length 1 m_fsr equ 14 ; frame sync relative timing m_fsp equ 15 ; frame sync polarity ; ssi status register bit flags m_if equ $3 ; serial input flag mask m_if0 equ 0 ; serial input flag 0 m_if1 equ 1 ; serial input flag 1 m_tfs equ 2 ; transmit frame sync flag m_rfs equ 3 ; receive frame sync flag m_tue equ 4 ; transmitter underrun error flag m_roe equ 5 ; receiver overrun error flag m_tde equ 6 ; transmit data register empty m_rdf equ 7 ; receive data register full ;------------------------------------------------------------------------ ; equates for exception processing ;------------------------------------------------------------------------ ; register addresses m_iprc equ $ffff ; interrupt priority register core m_iprp equ $fffe ; interrupt priority register peripheral ;------------------------------------------------------------------------ ; equates for timer ;------------------------------------------------------------------------ ; register addresses of timer0 m_tcsr0 equ $ff8f ; timer0 control/status register m_tlr0 equ $ff8e ; timer0 load reg m_tcpr0 equ $ff8d ; timer0 compare register m_tcr0 equ $ff8c ; timer0 count register example b-1 DSP56602 x i/o equates (continued)
x i/o equates motorola DSP56602 user? manual b-7 ; register addresses of timer1 m_tcsr1 equ $ff8b ; timer1 control/status register m_tlr1 equ $ff8a ; timer1 load reg m_tcpr1 equ $ff89 ; timer1 compare register m_tcr1 equ $ff88 ; timer1 count register ; register addresses of timer2 m_tcsr2 equ $ff87 ; timer2 control/status register m_tlr2 equ $ff86 ; timer2 load reg m_tcpr2 equ $ff85 ; timer2 compare register m_tcr2 equ $ff84 ; timer2 count register m_tplr equ $ff83 ; timer prescaler load register m_tpcr equ $ff82 ; timer prescalar count register ; timer control/status register bit flags m_te equ 0 ; timer enable m_toie equ 1 ; timer overflow interrupt enable m_tcie equ 2 ; timer compare interrupt enable m_tc equ $f0 ; timer control mask (tc0-tc3) m_inv equ 8 ; inverter bit m_trm equ 9 ; timer restart mode m_dir equ 10 ; direction bit m_di equ 11 ; data input m_do equ 12 ; data output m_tof equ 13 ; timer overflow flag m_tcf equ 14 ; timer compare flag m_pce equ 15 ; prescaled clock enable ; timer prescaler register bit flags m_ps equ $c000 ; prescaler source mask m_ps0 equ 14 ; prescaler source 0 m_ps1 equ 15 ; prescaler source 1 ; timer control bits m_tc0 equ 4 ; timer control 0 m_tc1 equ 5 ; timer control 1 m_tc2 equ 6 ; timer control 2 m_tc3 equ 7 ; timer control 3 example b-1 DSP56602 x i/o equates (continued)
b-8 DSP56602 user? manual motorola x i/o equates ;------------------------------------------------------------------------ ; equates for phase locked loop (pll) ;------------------------------------------------------------------------ ; register addresses of pll m_pctl0 equ $fffd ; pll control register 0 m_pctl1 equ $fffc ; pll control register 1 ; pll control register 0 (pctl0) m_mf equ $fff ; multiplication factor bits mask (mf0-mf11) m_pd equ $f000 ; predivider factor bits mask (pd3-pd0) m_pd03 equ $f000 ; predivider factor bits mask (pd3-pd0) ; pll control register 1 (pctl1) m_pd46 equ $0e00 ; predivider factor bits mask (pd6-pd4) m_df equ $7 ; division factor bits mask (df0-df2) m_xtlr equ 3 ; xtal range select bit m_xtld equ 4 ; xtal disable bit m_pstp equ 5 ; stop processing state bit m_pen equ 6 ; pll enable bit m_pcod equ 7 ; pll clock output disable bit ;------------------------------------------------------------------------ ; equates for biu ;------------------------------------------------------------------------ ; register addresses of biu m_bcr equ $fffa ; bus control register m_idr equ $fff9 ; id register ; register addresses of patch m_pa0 equ $fff8 ; patch address register 0 m_pa1 equ $fff7 ; patch address register 1 m_pa2 equ $fff6 ; patch address register 2 m_pa3 equ $fff5 ; patch address register 3 ; register addresses of bpmr m_bpmrg equ $fff4 ; bpmrg register m_bpmrl equ $fff3 ; bpmrl register m_bpmrh equ $fff2 ; bpmrh register ; bus control register m_bmw equ $1f ; memory wait control mask (bmw0-bmw4) example b-1 DSP56602 x i/o equates (continued)
x i/o equates motorola DSP56602 user? manual b-9 ;------------------------------------------------------------------------ ; equates for sr and omr ;------------------------------------------------------------------------ ; control and status bits in sr m_c equ 0 ; carry m_v equ 1 ; overflow m_z equ 2 ; zero m_n equ 3 ; negative m_u equ 4 ; unnormalized m_e equ 5 ; extension m_l equ 6 ; limit m_s equ 7 ; scaling bit m_i0 equ 8 ; interupt mask bit 0 m_i1 equ 9 ; interupt mask bit 1 m_s0 equ 10 ; scaling mode bit 0 m_s1 equ 11 ; scaling mode bit 1 m_fv equ 12 ; do-forever flag m_sm equ 13 ; arithmetic saturation m_rm equ 14 ; rounding mode m_lf equ 15 ; do-loop flag ; control and status bits in omr m_ma equ 0 ; operating mode a m_mb equ 1 ; operating mode b m_mc equ 2 ; operating mode c m_md equ 3 ; operating mode d m_ebd equ 4 ; external bus disable bit in omr m_pcd equ 5 ; pc relative logic disable m_sd equ 6 ; stop delay m_xys equ 8 ; stack extention space select m_eun equ 9 ; extended stack underflow flag m_eov equ 10 ; extended stack overflow flag m_wrp equ 11 ; extended stack wrap flag m_sen equ 12 ; stack extended enable m_ate equ 15 ; address tracing enable bit in omr. ;***************************************************************************** example b-1 DSP56602 x i/o equates (continued)
b-10 DSP56602 user? manual motorola x i/o equates b.2 DSP56602 interrupt equates example b-2 provides interrupt equates for the DSP56602. if bootstrap code is developed for the DSP56602 (for external bootstrap loading), this listing should be enclosed in a file titled intequ.asm for inclusion in the bootstrap executable. example b-2 DSP56602 interrupt equates ;------------------------------------------------------------------------ ; equates for DSP56602 interrupts ; reference: DSP56602 specifications revision 2.00 ; ; 1st update: june 6 1995 (creation, ; copied from dsp56301 and modified) by zvika r. ; ; last update: nov. 21 1995 (verified with verilog model and spec 2.00, ; changed to DSP56602 from dsp56601) by zvika r. ; ;***************************************************************************** page 132,55,0,0,0 opt mex ; DSP56602 equ 1 intequ ident 1,0 if @def(i_vec) ;leave user definition as is. else i_vec equ $0 endif ;------------------------------------------------------------------------ ; non-maskable interrupts ;------------------------------------------------------------------------ i_reset equ i_vec+$00 ; hardware reset i_stack equ i_vec+$02 ; stack error i_ill equ i_vec+$04 ; illegal instruction i_dbg equ i_vec+$06 ; debug request i_trap equ i_vec+$08 ; trap i_nmi equ i_vec+$0a ; non maskable interrupt
x i/o equates motorola DSP56602 user? manual b-11 ;------------------------------------------------------------------------ ; interrupt request pins ;------------------------------------------------------------------------ i_irqa equ i_vec+$10 ; irqa i_irqb equ i_vec+$12 ; irqb i_irqc equ i_vec+$14 ; irqc i_irqd equ i_vec+$16 ; irqd ;------------------------------------------------------------------------ ; timer interrupts ;------------------------------------------------------------------------ i_tim0c equ i_vec+$24 ; timer 0 compare i_tim0of equ i_vec+$26 ; timer 0 overflow i_tim1c equ i_vec+$28 ; timer 1 compare i_tim1of equ i_vec+$2a ; timer 1 overflow i_tim2c equ i_vec+$2c ; timer 2 compare i_tim2of equ i_vec+$2e ; timer 2 overflow ;------------------------------------------------------------------------ ; ssi interrupts ;------------------------------------------------------------------------ i_si0rd equ i_vec+$30 ; ssi0 receive data i_si0rde equ i_vec+$32 ; ssi0 receive data with exception status i_si0rls equ i_vec+$34 ; ssi0 receive last slot i_si0td equ i_vec+$36 ; ssi0 transmit data i_si0tde equ i_vec+$38 ; ssi0 transmit data with exception status i_si0tls equ i_vec+$3a ; ssi0 transmit last slot i_si1rd equ i_vec+$40 ; ssi1 receive data i_si1rde equ i_vec+$42 ; ssi1 receive data with exception status i_si1rls equ i_vec+$44 ; ssi1 receive last slot i_si1td equ i_vec+$46 ; ssi1 transmit data i_si1tde equ i_vec+$48 ; ssi1 transmit data with exception status i_si1tls equ i_vec+$4a ; ssi1 transmit last slot ;------------------------------------------------------------------------ ; host interrupts ;------------------------------------------------------------------------ i_hrdf equ i_vec+$60 ; host receive data full i_htde equ i_vec+$62 ; host transmit data empty i_hc equ i_vec+$64 ; default host command ;------------------------------------------------------------------------ ; interrupt ending address ;------------------------------------------------------------------------ i_intend equ i_vec+$ff ; last address of interrupt vector space example b-2 DSP56602 interrupt equates (continued)
b-12 DSP56602 user? manual motorola x i/o equates
motorola DSP56602 user? manual c-1 appendix c bsdl listing 1 0 0 0 0 1 1 0 1 1 0 0 1 1000 011 01 1001 1 0 0 0 0 1 1 0 1 1 0 0 1 0100101001011010 101001010110110 1010101010010111 0101001010010111 1000101010100100 0100010101011101 1010100011010101 1001011001110100 1 0 0 0 0 1 1 0 1 1 0 0 1 0100101001011010 1010101010110110 1010101010010111 0101001010010111 1000101010100100 0100010101011101 1010100011010101 1001011001110100
c-2 DSP56602 user? manual motorola bsdl listing c.1 DSP56602 bsdl listing . . . . . . . . . . . . . . . . . . . . . . . . . . . . c-3
bsdl listing motorola DSP56602 user? manual c-3 c.1 DSP56602 bsdl listing example c-1 provides the boundary scan description language (bsdl) listing for the DSP56602 in the thin quad flat pack (tqfp) package. example c-1 DSP56602 bsdl listing -- m o t o r o l a s s d t j t a g s o f t w a r e -- bsdl file generated: wed jun 5 12:34:06 1996 -- -- revision history: -- entity DSP56602a is generic (physical_pin_map : string := "tqfp144"); port ( sc02: inout bit; sc01: inout bit; sc00: inout bit; std0: inout bit; gpio0: inout bit; gpio1: inout bit; gpio2: inout bit; sck0: inout bit; srd0: inout bit; srd1: inout bit; sck1: inout bit; std1: inout bit; sc10: inout bit; sc11: inout bit; sc12: inout bit; tio0: inout bit; tio1: inout bit; tio2: inout bit; had: inout bit_vector(0 to 7); hreq: inout bit; modc: in bit; modb: in bit; moda: in bit; d: inout bit_vector(0 to 23); a: buffer bit_vector(0 to 15); extal: in bit; rd_: buffer bit; wr_: buffer bit; mcs_: buffer bit; pcap: linkage bit; reset_: in bit; at_: buffer bit; clkout: buffer bit;
c-4 DSP56602 user? manual motorola bsdl listing trst_: in bit; tdo: out bit; tdi: in bit; tck: in bit; tms: in bit; reserved: linkage bit_vector(0 to 11); sgnd: linkage bit_vector(0 to 1); svcc: linkage bit_vector(0 to 1); qgnd: linkage bit_vector(0 to 3); qvccl: linkage bit_vector(0 to 3); qvcch: linkage bit_vector(0 to 2); hgnd: linkage bit; hvcc: linkage bit; dgnd: linkage bit_vector(0 to 3); dvcc: linkage bit_vector(0 to 3); agnd: linkage bit_vector(0 to 3); avcc: linkage bit_vector(0 to 2); pvcc: linkage bit; pgnd1: linkage bit; pgnd: linkage bit; hack: inout bit; hds: inout bit; hrw: inout bit; cvcc: linkage bit; cgnd: linkage bit_vector(0 to 1); hcs: inout bit; ha9: inout bit; ha8: inout bit; has: inout bit; de_: inout bit; pinit: in bit; xtal: linkage bit; modd: in bit); use std_1149_1_1994.all; attribute component_conformance of DSP56602a : entity is "std_1149_1_1993"; attribute pin_map of DSP56602a : entity is physical_pin_map; constant tqfp144 : pin_map_string := "srd1: 1, " & "std1: 2, " & "sc02: 3, " & "sc01: 4, " & "de_: 5, " & "pinit: 6, " & "srd0: 7, " & example c-1 DSP56602 bsdl listing
bsdl listing motorola DSP56602 user? manual c-5 "svcc: (8, 25), " & "sgnd: (9, 26), " & "std0: 10, " & "sc10: 11, " & "sc00: 12, " & "gpio0: 13, " & "gpio1: 14, " & "gpio2: 15, " & "sck1: 16, " & "sck0: 17, " & "qvccl: (18, 56, 91, 126), " & "qgnd: (19, 54, 90, 127), " & "qvcch: (20, 57, 95), " & "hds: 21, " & "hrw: 22, " & "hack: 23, " & "hreq: 24, " & "tio2: 27, " & "tio1: 28, " & "tio0: 29, " & "hcs: 30, " & "ha9: 31, " & "ha8: 32, " & "has: 33, " & "had: (34, 35, 36, 37, 40, 41, 42, 43), " & "hvcc: 38, " & "hgnd: 39, " & "reset_: 44, " & "pvcc: 45, " & "pcap: 46, " & "pgnd: 47, " & "pgnd1: 48, " & "reserved: (50, 49, 51, 52, 61, 62, 63, 64, 69, 71, 98, 99), " & "xtal: 53, " & "extal: 55, " & "cgnd: (58, 66), " & "clkout: 59, " & "at_: 60, " & "cvcc: 65, " & "wr_: 67, " & "rd_: 68, " & "mcs_: 70, " & "a: (72, 73, 76, 77, 78, 79, 82, 83, 84, 85, 88, 89, 92, 93, 94, 97), " & "avcc: (74, 80, 86), " & "agnd: (75, 81, 87, 96), " & "d: (100, 101, 102, 105, 106, 107, 108, 109, 110, 113, 114, 115, 116, " & "117, 118, 121, 122, 123, 124, 125, 128, 131, 132, 133), " & "dvcc: (103, 111, 119, 129), " & "dgnd: (104, 112, 120, 130), " & example c-1 DSP56602 bsdl listing
c-6 DSP56602 user? manual motorola bsdl listing "modd: 134, " & "modc: 135, " & "modb: 136, " & "moda: 137, " & "trst_: 138, " & "tdo: 139, " & "tdi: 140, " & "tck: 141, " & "tms: 142, " & "sc12: 143, " & "sc11: 144 "; attribute tap_scan_in of tdi : signal is true; attribute tap_scan_out of tdo : signal is true; attribute tap_scan_mode of tms : signal is true; attribute tap_scan_reset of trst_ : signal is true; attribute tap_scan_clock of tck : signal is (20.0e6, both); attribute instruction_length of DSP56602a : entity is 4; attribute instruction_opcode of DSP56602a : entity is "extest (0000)," & "sample (0001)," & "idcode (0010)," & "clamp (0101)," & "highz (0100)," & "enable_once (0110)," & "debug_request (0111)," & "bypass (1111)"; attribute instruction_capture of DSP56602a : entity is "0001"; attribute idcode_register of DSP56602a : entity is "0001" & -- version "000110" & -- manufacturer's use "0000100010" & -- sequence number "00000001110" & -- manufacturer identity "1"; -- 1149.1 requirement attribute register_access of DSP56602a : entity is "once[8] (enable_once,debug_request)" ; attribute boundary_length of DSP56602a : entity is 124; attribute boundary_register of DSP56602a : entity is -- num cell port func safe [ccell dis rslt] "0 (bc_1, moda, input, x)," & "1 (bc_1, modb, input, x)," & "2 (bc_1, modc, input, x)," & "3 (bc_1, modd, input, x)," & example c-1 DSP56602 bsdl listing
bsdl listing motorola DSP56602 user? manual c-7 "4 (bc_6, d(23), bidir, x, 13, 1, z)," & "5 (bc_6, d(22), bidir, x, 13, 1, z)," & "6 (bc_6, d(21), bidir, x, 13, 1, z)," & "7 (bc_6, d(20), bidir, x, 13, 1, z)," & "8 (bc_6, d(19), bidir, x, 13, 1, z)," & "9 (bc_6, d(18), bidir, x, 13, 1, z)," & "10 (bc_6, d(17), bidir, x, 13, 1, z)," & "11 (bc_6, d(16), bidir, x, 13, 1, z)," & "12 (bc_6, d(15), bidir, x, 13, 1, z)," & "13 (bc_1, *, control, 1)," & "14 (bc_6, d(14), bidir, x, 13, 1, z)," & "15 (bc_6, d(13), bidir, x, 13, 1, z)," & "16 (bc_6, d(12), bidir, x, 13, 1, z)," & "17 (bc_6, d(11), bidir, x, 26, 1, z)," & "18 (bc_6, d(10), bidir, x, 26, 1, z)," & "19 (bc_6, d(9), bidir, x, 26, 1, z)," & -- num cell port func safe [ccell dis rslt] "20 (bc_6, d(8), bidir, x, 26, 1, z)," & "21 (bc_6, d(7), bidir, x, 26, 1, z)," & "22 (bc_6, d(6), bidir, x, 26, 1, z)," & "23 (bc_6, d(5), bidir, x, 26, 1, z)," & "24 (bc_6, d(4), bidir, x, 26, 1, z)," & "25 (bc_6, d(3), bidir, x, 26, 1, z)," & "26 (bc_1, *, control, 1)," & "27 (bc_6, d(2), bidir, x, 26, 1, z)," & "28 (bc_6, d(1), bidir, x, 26, 1, z)," & "29 (bc_6, d(0), bidir, x, 26, 1, z)," & "30 (bc_1, a(15), output2, x)," & "31 (bc_2, a(14), output2, x)," & "32 (bc_2, a(13), output2, x)," & "33 (bc_2, a(12), output2, x)," & "34 (bc_2, a(11), output2, x)," & "35 (bc_2, a(10), output2, x)," & "36 (bc_2, a(9), output2, x)," & "37 (bc_2, a(8), output2, x)," & "38 (bc_2, a(7), output2, x)," & "39 (bc_2, a(6), output2, x)," & -- num cell port func safe [ccell dis rslt] "40 (bc_2, a(5), output2, x)," & "41 (bc_2, a(4), output2, x)," & "42 (bc_2, a(3), output2, x)," & "43 (bc_2, a(2), output2, x)," & "44 (bc_2, a(1), output2, x)," & "45 (bc_2, a(0), output2, x)," & "46 (bc_2, mcs_, output2, x)," & "47 (bc_2, rd_, output2, x)," & "48 (bc_2, wr_, output2, x)," & "49 (bc_2, at_, output2, x)," & "50 (bc_2, clkout, output2, x)," & example c-1 DSP56602 bsdl listing
c-8 DSP56602 user? manual motorola bsdl listing "51 (bc_1, extal, input, x)," & "52 (bc_1, reset_, input, x)," & "53 (bc_1, *, control, 1)," & "54 (bc_6, had(0), bidir, x, 53, 1, z)," & "55 (bc_1, *, control, 1)," & "56 (bc_6, had(1), bidir, x, 55, 1, z)," & "57 (bc_1, *, control, 1)," & "58 (bc_6, had(2), bidir, x, 57, 1, z)," & "59 (bc_1, *, control, 1)," & -- num cell port func safe [ccell dis rslt] "60 (bc_6, had(3), bidir, x, 59, 1, z)," & "61 (bc_1, *, control, 1)," & "62 (bc_6, had(4), bidir, x, 61, 1, z)," & "63 (bc_1, *, control, 1)," & "64 (bc_6, had(5), bidir, x, 63, 1, z)," & "65 (bc_1, *, control, 1)," & "66 (bc_6, had(6), bidir, x, 65, 1, z)," & "67 (bc_1, *, control, 1)," & "68 (bc_6, had(7), bidir, x, 67, 1, z)," & "69 (bc_1, *, control, 1)," & "70 (bc_6, has, bidir, x, 69, 1, z)," & "71 (bc_1, *, control, 1)," & "72 (bc_6, ha8, bidir, x, 71, 1, z)," & "73 (bc_1, *, control, 1)," & "74 (bc_6, ha9, bidir, x, 73, 1, z)," & "75 (bc_1, *, control, 1)," & "76 (bc_6, hcs, bidir, x, 75, 1, z)," & "77 (bc_1, *, control, 1)," & "78 (bc_6, tio0, bidir, x, 77, 1, z)," & "79 (bc_1, *, control, 1)," & -- num cell port func safe [ccell dis rslt] "80 (bc_6, tio1, bidir, x, 79, 1, z)," & "81 (bc_1, *, control, 1)," & "82 (bc_6, tio2, bidir, x, 81, 1, z)," & "83 (bc_1, *, control, 1)," & "84 (bc_6, hreq, bidir, x, 83, 1, z)," & "85 (bc_1, *, control, 1)," & "86 (bc_6, hack, bidir, x, 85, 1, z)," & "87 (bc_1, *, control, 1)," & "88 (bc_6, hrw, bidir, x, 87, 1, z)," & "89 (bc_1, *, control, 1)," & "90 (bc_6, hds, bidir, x, 89, 1, z)," & "91 (bc_1, *, control, 1)," & "92 (bc_6, sck0, bidir, x, 91, 1, z)," & "93 (bc_1, *, control, 1)," & "94 (bc_6, sck1, bidir, x, 93, 1, z)," & "95 (bc_1, *, control, 1)," & "96 (bc_6, gpio2, bidir, x, 95, 1, z)," & "97 (bc_1, *, control, 1)," & example c-1 DSP56602 bsdl listing
bsdl listing motorola DSP56602 user? manual c-9 "98 (bc_6, gpio1, bidir, x, 97, 1, z)," & "99 (bc_1, *, control, 1)," & -- num cell port func safe [ccell dis rslt] "100 (bc_6, gpio0, bidir, x, 99, 1, z)," & "101 (bc_1, *, control, 1)," & "102 (bc_6, sc00, bidir, x, 101, 1, z)," & "103 (bc_1, *, control, 1)," & "104 (bc_6, sc10, bidir, x, 103, 1, z)," & "105 (bc_1, *, control, 1)," & "106 (bc_6, std0, bidir, x, 105, 1, z)," & "107 (bc_1, *, control, 1)," & "108 (bc_6, srd0, bidir, x, 107, 1, z)," & "109 (bc_1, pinit, input, x)," & "110 (bc_1, *, control, 1)," & "111 (bc_6, de_, bidir, x, 110, 1, z)," & "112 (bc_1, *, control, 1)," & "113 (bc_6, sc01, bidir, x, 112, 1, z)," & "114 (bc_1, *, control, 1)," & "115 (bc_6, sc02, bidir, x, 114, 1, z)," & "116 (bc_1, *, control, 1)," & "117 (bc_6, std1, bidir, x, 116, 1, z)," & "118 (bc_1, *, control, 1)," & "119 (bc_6, srd1, bidir, x, 118, 1, z)," & -- num cell port func safe [ccell dis rslt] "120 (bc_1, *, control, 1)," & "121 (bc_6, sc11, bidir, x, 120, 1, z)," & "122 (bc_1, *, control, 1)," & "123 (bc_6, sc12, bidir, x, 122, 1, z)"; end DSP56602a; example c-1 DSP56602 bsdl listing
c-10 DSP56602 user? manual motorola bsdl listing
motorola DSP56602 user? manual d-1 appendix d programmer? reference
d-2 DSP56602 user? manual motorola programmer? reference d.1 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . d-3 d.2 instruction set summary. . . . . . . . . . . . . . . . . . . . . . . . d-3 d.3 interrupt, vector, and address tables . . . . . . . . d-14 d.4 programmer? sheets . . . . . . . . . . . . . . . . . . . . . . . . . . d-23
programmer? reference motorola DSP56602 user? manual d-3 d.1 introduction the following pages provide a set of reference tables and programming sheets that are intended to simplify programming the DSP56602. the programming sheets provide room to write in the value of each bit and the hexadecimal value for each register. the programmer can photocopy these sheets. d.2 instruction set summary the following tables provide a brief summary of the instruction set for the DSP56602. table d-1 , table d-2 , and table d-3 provide a key to the abbreviations in table d-4 , the instruction set summary table. for complete instruction set details, see appendix a of the dsp56600 family manual (dsp56600fm/ad) . table d-1 program word and timing symbols column description and symbols p parallel move p parallel move n no parallel move not applicable t instruction clock cycle counts (add one cycle for each symbol in column) u pre-update a long absolute i long immediate table d-2 condition code register (ccr) symbols symbol description s scaling bit indicating data growth is detected l limit bit indicating arithmetic overflow and/or data limiting e extension bit indicating if the integer portion is in use u unnormalized bit indicating if the result is unnormalized n negative bit indicating if bit 35 (or 31) of the result is set
d-4 DSP56602 user? manual motorola programmer? reference z zero bit indicating if the result equals 0 v overflow bit indicating if arithmetic overflow has occurred in the result c carry bit indicating if a carry or borrow occurred in the result table d-3 condition code register notation notation description * bit is set or cleared according to the standard definition by the result of the operation bit is not affected by the operation 0 bit is always cleared by the operation 1 bit is always set by the operation u undefined ? bit is set or cleared according to the special computation definition by the result of the operation table d-4 instruction set summary mnemonic syntax p t ccr sleunzvc abs abs d p 1 * * * * * * * adc adc s,d p 1 * * * * * * * * add add s,d p 1 * * * * * * * * add #iiiiii,d 2 * * * * * * * * add #iii,d 1 * * * * * * * * addl addl s,d p 1 * * * * * * ? * addr addr s,d p 1 * * * * * * * * and and s,d p 1 * ? ? 0 and #iiiiii,d 2 * ? ? 0 table d-2 condition code register (ccr) symbols (continued) symbol description
programmer? reference motorola DSP56602 user? manual d-5 and and #iii,d 1 * ? ? 0 andi andi ee 3 ? ? ? ? ? ? ? ? asl asl s,d p 1 * * * * * * ? ? asl #ii,s,d 1 * * * * * * ? ? asl sss,s,d 1 * * * * * * ? ? asr asr s,d p 1 * * * * * * 0 ? asr sss,s,d 1 * * * * * * 0 ? asr #ii,s,d 1 * * * * * * 0 ? bcc bcc (pc + rn) 4 bcc (pc + aa) 4 bchg bchg #bbbb , s: 2 ? ? ? ? ? ? ? ? bchg #bbbb , s: 2 + u + a ? ? ? ? ? ? ? ? bchg #bbbb , s: 2 ? ? ? ? ? ? ? ? bchg #bbbb , s: 2 ? ? ? ? ? ? ? ? bchg #bbbb, dddddd 2 ? ? ? ? ? ? ? ? bclr bclr #bbbb , s: 2 ? ? ? ? ? ? ? ? bclr #bbbb , s: 2 + u + a ? ? ? ? ? ? ? ? bclr #bbbb , s: 2 ? ? ? ? ? ? ? ? bclr #bbbb , s: 2 ? ? ? ? ? ? ? ? bclr #bbbb , dddddd 2 ? ? ? ? ? ? ? ? bra bra (pc + rn) 4 bra (pc + aa) 4 brkcc brkcc 5 table d-4 instruction set summary (continued) mnemonic syntax p t ccr sleunzvc
d-6 DSP56602 user? manual motorola programmer? reference bscc bscc (pc + rn) 4 bscc (pc + aa) 4 bset bset #bbbb,s: 2 ? ? ? ? ? ? ? ? bset #bbbb, s: 2 + u + a ? ? ? ? ? ? ? ? bset #bbbb, s: 2 ? ? ? ? ? ? ? ? bset #bbbb , dddddd 2 ? ? ? ? ? ? ? ? bset #bbbb , s: 2 ? ? ? ? ? ? ? ? bsr bsr (pc + rn) 4 bsr (pc + aa) 4 btst btst #bbbb,s: 2 * * ? btst #bbb ,s: 2 + u + a * * ? btst #bbbb,s: 2 * * ? btst #bbbb , dddddd 2 * * ? btst #bbbb,s: 2 * * ? clb clb s,d 1 ? ? 0 clr clr d p 1 * * 0 1 0 1 0 cmp cmp s1,s2 p 1 * * * * * * * * cmp #iiiiii,d 2 * * * * * * * * cmp #iii,d 1 * * * * * * * * cmpm cmpm s1,s2 p 1 * * * * * * * * cmpu cmpu ggg,d 1 * ? 0 * debug debug 1 debugcc debugcc 5 table d-4 instruction set summary (continued) mnemonic syntax p t ccr sleunzvc
programmer? reference motorola DSP56602 user? manual d-7 dec dec 1 * * * * * * * div div 1 ? ? ? dmac dmac s1,s2,d (ss,su,uu) n 1 * * * * * * do do #xxx,aaaa 5 ? ? do dddddd,aaaa 5 ? ? do s:,aaaa 5 + u ? ? do s:,aaaa 5 ? ? do forever do forever , (aaaa) 4 enddo enddo 1 eor eor s,d p 1 * * ? ? 0 eor #iiiiii,d 2 * * ? ? 0 eor #iii,d 1 * * ? ? 0 extract extract sss,s,d 1 * * * * 0 0 extract #iiii,s,d 2 * * * * 0 0 extractu extractu sss,s,d 1 * * * * 0 0 extractu #iiii,s,d 2 * * * * 0 0 ifcc ifcc 1 ifcc(.u) ifcc(.u) 1 ? ? ? ? ? ? ? ? illegal illegal 5 inc inc d 1 * * * * * * * insert insert sss,qqq,d 1 * * * * 0 0 insert #iiii,qqq,d 2 * * * * 0 0 table d-4 instruction set summary (continued) mnemonic syntax p t ccr sleunzvc
d-8 DSP56602 user? manual motorola programmer? reference jcc jcc aa 4 jcc ea 4 jclr jclr #bbbb,s:,aaaa 4 + u * * jclr #bbbb,s:,aaaa 4 * * jclr #bbbb ,s:,aaaa 4 * * jclr #bbbb,dddddd,aaaa 4 * * jclr #bbbb, s:,aaaa 4 * * jmp jmp aa 3 jmp ea 3 + u + a jscc jscc aa 4 jscc ea 4 jsclr jsclr #bbbb,s:,aaaa 4 * * jsclr #bbbb , s:,aaaa 4 + u * * jsclr #bbbb , s:,aaaa 4 * * jsclr #bbbb, dddddd,aaaa 4 * * jsclr #bbbb , s:,aaaa 4 * * jset jset #bbbb , s:,aaaa 4 * * jset #bbbb , s:,aaaa 4 + u * * jset #bbbb , s:,aaaa 4 * * jset #bbbb, dddddd,aaaa 4 * * jset #bbbb , s:,aaaa 4 * * jsr jsr aa 3 jsr ea 3 + u + a table d-4 instruction set summary (continued) mnemonic syntax p t ccr sleunzvc
programmer? reference motorola DSP56602 user? manual d-9 jsset jsset #bbbb,s:,aaaa 4 * * jsset #bbbb,s:,aaaa 4 + u * * jsset #bbbb,s:,aaaa 4 * * jsset #bbbb, dddddd,aaaa 4 * * jsset #bbbb,s:,aaaa 4 * * lra lra (pc + rn) ? 0ddddd 3 lra (pc + aaaa) ? 0ddddd 3 lsl lsl d p 1 * * ? ? 0 ? lsl sss,d 1 * * ? ? 0 ? lsl #ii,d 1 * * ? ? 0 ? lsr lsr d p 1 * * ? ? 0 ? lsr #ii,d 1 * * ? ? 0 ? lsr sss,d 1 * * ? ? 0 ? lua, lea lua ea ? 0ddddd 3 lua (rn + aa) ? 01dddd 3 mac mac ?2**s,qq,d 1 * * * * * * * mac s1,s2,d 1 * * * * * * * mac (su,uu) mac s1,s2,d n 1 * * * * * * maci maci ?#iiiiii,qq,d 2 * * * * * * macr macr ?**s,qq,d 1 * * * * * * * macri macri ?#iiiiii,qq,d 2 * * * * * * max max a,b p 1 * * ? maxm maxm a,b p 1 * * ? table d-4 instruction set summary (continued) mnemonic syntax p t ccr sleunzvc
d-10 DSP56602 user? manual motorola programmer? reference merge merge sss,d 1 ? ? 0 move no parallel data move (dalu) n 1 move #xx ? ddddd 1 move ddddd ? ddddd 1 * * u move 1 move s:,ddddd 1+u+a+i * * move s:,ddddd 1 * * move s:,dddd 2 * * move s:,dddddd ? ** move d ? x y:,yy 1+u+a+i * * move x:,xx & d ? y 1+u+a+i * * move a ? x: x0 a 1 + u * * move b ? x: x0 b 1 + u * * move y0 ? a a y: 1 + u * * move y0 ? b b y: 1 + u * * move l:,lll 1 + u + a * * move l:,lll 1 * * move x:,xx & y:,yy ? ** movec movec #xx ? 1ddddd 1 ? ? ? ? ? ? ? ? movec s:,1ddddd 1+u+a+i ? ? ? ? ? ? ? ? movec s:,1ddddd 1 ? ? ? ? ? ? ? ? movec dddddd, 1ddddd 1 ? ? ? ? ? ? ? ? table d-4 instruction set summary (continued) mnemonic syntax p t ccr sleunzvc
programmer? reference motorola DSP56602 user? manual d-11 movem movem p:,dddddd 6 + u + a ? ? ? ? ? ? ? ? movem p:,dddddd 6 ? ? ? ? ? ? ? ? movep movep s:,s: 2 + u + a ? ? ? ? ? ? ? ? movep s:,p: 6 + u + a ? ? ? ? ? ? ? ? movep s:,dddddd 1 ? ? ? ? ? ? ? ? movep x:,s: 2 + u + a ? ? ? ? ? ? ? ? movep y:,s: 2 + u + a ? ? ? ? ? ? ? ? movep x:,dddddd 1 ? ? ? ? ? ? ? ? movep y:,dddddd 1 ? ? ? ? ? ? ? ? movep s:,p: 6 + u + a ? ? ? ? ? ? ? ? mpy mpy ?2**s,qq,d 1 * * * * * * * mpy(su,uu) mpy s1,s2,d (su,uu) 1 * * * * * * mpyi mpyi ?#iiiiii,qq,d 2 * * * * * * mpyr mpyr ?2**s,qq,d 1 * * * * * * * mpyri mpyri ?#iiiiii,qq,d 2 * * * * * * neg neg d p 1 * * * * * * * nop nop 1 normf normf sss,d 1 * * * * * ? not not d p 1 * * ? ? 0 or or sd p 1 * * ? ? 0 or #iiiiii,d 2 * * ? ? 0 or #iii,d 1 * * ? ? 0 ori ori ee 3 ? ? ? ? ? ? ? ? table d-4 instruction set summary (continued) mnemonic syntax p t ccr sleunzvc
d-12 DSP56602 user? manual motorola programmer? reference rep rep #xxx 5 * * rep dddddd 5 * * rep s: 5 + u * * rep s: 5 * * reset reset 7 rnd rnd d p 1 * * * * * * * rol rol d p 1 * * ? ? 0 ? ror ror d p 1 * * ? ? 0 ? rti rti 3 ? ? ? ? ? ? ? ? rts rts 3 sbc sbc s,d p 1 * * * * * * * * stop stop 10 sub sub s,d p 1 * * * * * * * * sub #iiiiii,d 2 * * * * * * * * sub #iii,d 1 * * * * * * * * subl subl s,d p 1 * * * * * * ? * subr subr s,d p 1 * * * * * * * * tcc tcc jjj ? d ttt ttt 1 tcc jjj ? d 1 tcc ttt ? ttt 1 tfr tfr s,d p 1 * * trap trap 9 trapcc trapcc 9 table d-4 instruction set summary (continued) mnemonic syntax p t ccr sleunzvc
programmer? reference motorola DSP56602 user? manual d-13 tst tst s p 1 * * * * * * 0 vsl vsl s,i,l:ea 1 + u + a wait wait 10 table d-4 instruction set summary (continued) mnemonic syntax p t ccr sleunzvc
d-14 DSP56602 user? manual motorola programmer? reference d.3 interrupt, vector, and address tables table d-5 interrupt sources interrupt starting address ipl interrupt source vba:$00 3 hardware reset vba:$02 3 stack error vba:$04 3 illegal instruction vba:$06 3 debug request interrupt vba:$08 3 trap vba:$0a 3 nmi vba:$0c 3 (reserved) vba:$0e 3 (reserved) vba:$10 0? irqa vba:$12 0? irqb vba:$14 0? irqc vba:$16 0? irqd vba:$18 0? (reserved) vba:$1a 0? (reserved) vba:$1c 0? (reserved) vba:$1e 0? (reserved) vba:$20 0? (reserved) vba:$22 0? (reserved) vba:$24 0? timer 0 compare vba:$26 0? timer 0 overflow vba:$28 0? timer 1 compare vba:$2a 0? timer 1 overflow vba:$2c 0? timer 2 compare
programmer? reference motorola DSP56602 user? manual d-15 vba:$2e 0? timer 2 overflow vba:$30 0? ssi0 receive data vba:$32 0? ssi0 receive data with exception status vba:$34 0? ssi0 receive last slot vba:$36 0? ssi0 transmit data vba:$38 0? ssi0 transmit data with exception status vba:$3a 0? ssi0 transmit last slot vba:$3c 0? (reserved) vba:$3e 0? (reserved) vba:$40 0? ssi1 receive data vba:$42 0? ssi1 receive data with exception status vba:$44 0? ssi1 receive last slot vba:$46 0? ssi1 transmit data vba:$48 0? ssi1 transmit data with exception status vba:$4a 0? ssi0 transmit last slot vba:$4c 0? (reserved) vba:$4e 0? (reserved) vba:$60 0? host receive data full vba:$62 0? host transmit data empty vba:$64 0? default host command vba:$66 0? (reserved) . . . . . . . . . vba:$fe (reserved) table d-5 interrupt sources (continued) interrupt starting address ipl interrupt source
d-16 DSP56602 user? manual motorola programmer? reference table d-6 interrupt source priorities within an ipl priority interrupt source level 3 (nonmaskable) highest hardware reset stack error illegal instruction debug request interrupt trap lowest nmi levels 0, 1, 2 (maskable) highest irqa (external interrupt) irqb (external interrupt) irqc (external interrupt) irqd (external interrupt) host command interrupt host transmit data full host receive data empty ssi0 rx data with exception interrupt ssi0 rx data interrupt ssi0 receive last slot interrupt ssi0 tx data with exception interrupt ssi0 transmit last slot interrupt ssi0 tx data interrupt ssi1 rx data with exception interrupt ssi1 rx data interrupt ssi1 receive last slot interrupt
programmer? reference motorola DSP56602 user? manual d-17 ssi1 tx data with exception interrupt ssi1 transmit last slot interrupt ssi1 tx data interrupt timer 0 overflow interrupt timer 0 compare interrupt timer 1 overflow interrupt timer 1 compare interrupt timer 2 overflow interrupt lowest timer 2 compare interrupt table d-7 internal i/o memory map peripheral address register name reset value pic $ffff ipr-c?nterrupt priority register?ore $0000 $fffe ipr-p?nterrupt priority register?eripheral $0000 pll $fffd pctl0?ll control register $0000 $fffc pctl1?ll control register $0000 once $fffb ogdbr?nce gdb register $0000 biu $fffa bcr?us control register $001f $fff9 idr?d register $1602 patch $fff8 par0?atch 0 register uninitialized $fff7 par1?atch 1 register uninitialized $fff6 par2?atch 2 register uninitialized $fff5 par3?atch 3 register uninitialized bpmr $fff4 bpmrg?us switch program memory register (24 bits) uninitialized table d-6 interrupt source priorities within an ipl (continued) priority interrupt source
d-18 DSP56602 user? manual motorola programmer? reference bpmr $fff3 bpmrl?us switch program memory register low (16 bits) uninitialized $fff2 bpmrh?us switch program memory register high (16 bits) uninitialized (reserved) $fff1 (reserved) uninitialized $fff0 (reserved) uninitialized $ffef (reserved) uninitialized $ffee (reserved) uninitialized $ffed (reserved) uninitialized $ffec (reserved) uninitialized $ffeb (reserved) uninitialized $ffea (reserved) uninitialized $ffe9 (reserved) uninitialized $ffe8 (reserved) uninitialized $ffe7 (reserved) uninitialized $ffe6 (reserved) uninitialized $ffe5 (reserved) uninitialized $ffe4 (reserved) uninitialized $ffe3 (reserved) uninitialized $ffe2 (reserved) uninitialized $ffe1 (reserved) uninitialized $ffe0 (reserved) uninitialized $ffdf (reserved) uninitialized $ffde (reserved) uninitialized $ffdd (reserved) uninitialized table d-7 internal i/o memory map (continued) peripheral address register name reset value
programmer? reference motorola DSP56602 user? manual d-19 (reserved) $ffdc (reserved) uninitialized $ffdb (reserved) uninitialized $ffda (reserved) uninitialized $ffd9 (reserved) uninitialized $ffd8 (reserved) uninitialized $ffd7 (reserved) uninitialized $ffd6 (reserved) uninitialized $ffd5 (reserved) uninitialized $ffd4 (reserved) uninitialized $ffd3 (reserved) uninitialized $ffd2 (reserved) uninitialized $ffd1 (reserved) uninitialized $ffd0 (reserved) uninitialized $ffcf (reserved) $0000 $ffce (reserved) $0000 $ffcd (reserved) $0000 $ffcc (reserved) $0000 $ffcb (reserved) $0000 $ffca (reserved) $0000 hi08 $ffc9 hdr?i08 data register uninitialized $ffc8 hddr?i08 data direction register $0000 $ffc7 htx?i08 transmit data register $0000 $ffc6 hrx?i08 receive data register uninitialized $ffc5 hbar ?i08 base address register $0080 $ffc4 hpcr?i08 port control register $0000 table d-7 internal i/o memory map (continued) peripheral address register name reset value
d-20 DSP56602 user? manual motorola programmer? reference hi08 $ffc3 hsr?i08 status register $0002 $ffc2 hcr?i08 control register $0000 (reserved) $ffc1 (reserved) $0000 $ffc0 (reserved) $0000 ssi0 $ffbf pcrc?si 0 port control register $0000 $ffbe prrc?si 0 gpio direction register $0000 $ffbd pdrc?si 0 gpio data register $0000 $ffbc tx0?si 0 transmit data register $0000 $ffbb tsr0?si 0 time slot register $0000 $ffba rx0?si 0 receive data register uninitialized $ffb9 ssisr0?si 0 status register $0040 $ffb8 crc0?si 0 control register c $0000 $ffb7 crb0?si 0 control register b $0000 $ffb6 cra0?si 0 control register a $0000 (reserved) $ffb5 (reserved) $0000 $ffb4 (reserved) $0000 $ffb3 (reserved) $0000 $ffb2 (reserved) $0000 $ffb1 (reserved) $0000 $ffb0 (reserved) $0000 ssi1 $ffaf pcrd?si 1 port control register $0000 $ffae prrd?si 1 gpio direction register $0000 $ffad pdrd?si 1 gpio data register $0000 $ffac tx1?si 1 transmit data register $0000 $ffab tsr1?si 1 time slot register $0000 table d-7 internal i/o memory map (continued) peripheral address register name reset value
programmer? reference motorola DSP56602 user? manual d-21 ssi1 $ffaa rx1?si 1 receive data register uninitialized $ffa9 ssisr1?si 1 status register $0040 $ffa8 crc1?si 1 control register c $0000 $ffa7 crb1?si 1 control register b $0000 $ffa6 cra1?si 1 control register a $0000 (reserved) $ffa5 (reserved) $0000 $ffa4 (reserved) $0000 $ffa3 (reserved) $0000 $ffa2 (reserved) $0000 $ffa1 (reserved) $0000 $ffa0 (reserved) $0000 gpio $ff9f pcre?pio control register $0000 $ff9e prre?pio direction register $0000 $ff9d pdre?pio data register $0007 triple timer $ff8f tcsr0?imer 0 control/status register $0000 $ff8e tlr0?imer 0 load register $0000 $ff8d tcpr0?imer 0 compare register $0000 $ff8c tcr0?imer 0 count register $0000 $ff8b tcsr1?imer 1 control/status register $0800 $ff8a tlr1?imer 1 load register $0000 $ff89 tcpr1?imer 1 compare register $0000 $ff88 tcr1?imer 1 count register $0000 $ff87 tcsr2?imer 2 control/status register $0800 $ff86 tlr2?imer 2 load register $0000 $ff85 tcpr2?imer 2 compare register $0000 table d-7 internal i/o memory map (continued) peripheral address register name reset value
d-22 DSP56602 user? manual motorola programmer? reference triple timer $ff84 tcr2?imer 2 count register $0000 $ff83 tplr?imer prescaler load register $0000 $ff82 tpcr?imer prescaler count register uninitialized (reserved) $ff81 (reserved) $0000 $ff80 (reserved) $0000 table d-7 internal i/o memory map (continued) peripheral address register name reset value
programmer? reference motorola DSP56602 user? manual d-23 d.4 programmer? sheets the following pages provide programmer? sheets that are intended to simplify programming the various registers in the dsp56603. the programmer? sheets provide room to write in the value of each bit and the hexadecimal value for each register. the programmer can photocopy these sheets. the programmer? sheets are provided in the same order as the sections in this document. table d-8 lists the sets of programmer? sheets, the registers described in the sheets, and the pages in this appendix where the sheets are located. table d-8 list of programmer? sheets type of register register page cpu jtag instruction register d-26 jtag bypass register d-26 jtag id register d-26 omr?perating mode register d-27 sr?tatus register d-28 ipr-c?nterrupt priority register (core) d-29 ipr-p?nterrupt priority register (peripheral ) d-30 bcr?bus control register d-31 idr?dentification register d-31 parn?atch registers d-32 bpmrg?us switch program memory register d-33 bpmrl?us switch program memory register low d-33 bpmrh?us switch program memory register high d-33 pll pctl0?ll control register 0 d-34 pctl1?ll control register 1 d-34 hi08 hsr?i08 status register d-35 hcr?i08 control register d-35 hpcr?i08 port control register d-36
d-24 DSP56602 user? manual motorola programmer? reference hi08 hddr?i08 data direction register d-37 hdr?i08 data register d-37 hrx?i08 receive data register d-37 htx?i08 transmit data register d-37 hbar?i08 base address register d-37 icr?nterface control register d-38 isr?nterface status register d-38 cvr?ontrol vector register d-39 ivr?nterrupt vector register d-39 ssi0 cra0?si0 control register a d-40 crb0?si0 control register b d-40 crc0?si0 control register c d-41 ssisr0?si0 status register d-42 rx0?si0 receive register d-42 tsr0?si0 time slot register d-42 tx0?si0 transmit register d-42 pcrc?si0 port c control register d-43 pdrc?si0 port c data register d-43 prrc?si0 port c data direction register d-43 ssi1 cra1?si1 control register a d-44 crb1?si1 control register b d-44 crc1?si1 control register c d-45 ssisr1?si1 status register d-46 rx1?si1 receive register d-46 tsr1?si1 time slot register d-46 table d-8 list of programmer? sheets (continued) type of register register page
programmer? reference motorola DSP56602 user? manual d-25 ssi1 tx1?si1 transmit register d-46 pcrd?si1 port d control register d-47 pdrd?si1 port d data register d-47 prrd?si1 port d data direction register d-47 gpio pcre?pio port control register d-48 pdre?pio port data register d-48 prre?pio port data direction register d-48 timers tplr?imer prescaler load register d-49 tpcr?imer prescaler count register d-49 timer0 tcsr0?imer 0 control/status register d-50 tlr0?imer 0 load register d-50 tcpr0?imer 0 compare register d-50 tcr0?imer 0 count register d-50 timer1 tcsr1?imer 1 control/status register d-51 tlr1?imer 1 load register d-51 tcpr1?imer 1 compare register d-51 tcr1?imer 1 count register d-51 timer2 tcsr2?imer 2 control/status register d-52 tlr2?imer 2 load register d-52 tcpr2?imer 2 compare register d-52 tcr2?imer 2 count register d-52 table d-8 list of programmer? sheets (continued) type of register register page
d-26 DSP56602 user? manual motorola programmer? reference sheet 1 of 8 application: date: programmer: cpu jtag id register jtag instruction register reset = $2 read only read/write jtag bypass register reset = $0 read/write inv inv inv inv inv inv inv inv 76543210 76543210 0 b2 b3 b1 b0 3210 msk msk msk msk 3210 11 10 9 8 msk msk msk msk 7654 15 14 13 12 inv inv inv inv inv inv inv inv 76543210 23 22 21 20 19 18 17 16 msk msk msk msk 3210 27 26 25 24 msk msk msk msk 7654 31 30 29 28 reset = $1182201d 0 0 $0 $1 $2 $8 $d $1 $1 $2 1 00 01 00 10 00 00 1 0 00 0 0 00 10 01 01 11 0 aa1106a
programmer? reference motorola DSP56602 user? manual d-27 mc mb ma mode reset vector 0 0 0 0?xtended $0400 0 0 1 1?ormal $0800 0 1 0 2?ormal $0800 0 1 1 3?ormal $0800 1 0 0 4?ormal $0800 1 0 1 5?ormal $0800 1 1 0 6?ormal $0800 1 1 1 7?ormal $0800 operating mode read/write reset = $0300 * = reserved, program as 0 eom com extended operating chip operating ate 15 mb mc ma ebd md sd pcd 6543210 xys eov eun 10987 sen wrp 14 13 12 11 register (omr) * 0 * 0 ate description 0 address trace disabled 1 address trace enabled cpu sen description 0 stack extension disabled 1 stack extension enabled extended stack overflow flag extended stack underflow flag extended stack wrap flag xys description 0 stack extension mapped to x memory 1 stack extension mapped to y memory sd description 0 128 k clock cycle delay 1 16 clock cycle delay ebd description 0 external bus controller enabled 1 external bus controller disabled pcd description 0 pc relative instructions enabled 1 pc relative instructions disabled mode register mode register * 0 sheet 2 of 8 application: date: programmer: aa1106b
d-28 DSP56602 user? manual motorola programmer? reference i1 i0 exceptions permitted exceptions masked 0 0 ipl 0, 1, 2, 3 none 0 1 ipl 1, 2, 3 ipl 0 1 0 ipl 2, 3 ipl 0, 1 1 1 ipl 3 ipl 0, 1, 2 status register read/write reset = $0300 mr ccr mode register condition code register carry overflow zero negative unnormalized extension limit scaling lf 15 v zc un le 6543210 i0 s0 i1 10987 fv s1 14 13 12 11 (sr) rm rounding mode 0 convergent rounding 1 two?-complement rounding cpu rm sm s s1 s0 rounding bit scaling mode 0 0 15 no scaling 0 1 16 scale down? bit arithmetic right shift 1 0 14 scale up? bit arithmetic left shift 1 1 (reserved) do forever flag do loop flag sm arithmetic saturation mode 0 convergent rounding 1 automatic 32-bit saturation selected sheet 3 of 8 application: date: programmer: aa1106c
programmer? reference motorola DSP56602 user? manual d-29 ial2 ial1 icl0 ibl2 ibl1 icl1 ibl0 interrupt priority x:$ffff reset = $0000 cpu * = reserved, program as 0 ial0 ial2 ial1 ial0 irqa mode trigger mode 0 0 0 irqa disabled, no ipl level-triggered 0 0 1 irqa enabled, ipl = 0 level-triggered 0 1 0 irqa enabled, ipl = 1 level-triggered 0 1 1 irqa enabled, ipl = 2 level-triggered 1 0 0 irqa disabled, no ipl negative-edge triggered 1 0 1 irqa enabled, ipl = 0 negative-edge triggered 1 1 0 irqa enabled, ipl = 1 negative-edge triggered 1 1 1 irqa enabled, ipl = 2 negative-edge triggered * 0 15 6543210 10987 14 13 12 11 * 0 * 0 register?ore (ipr?) * 0 icl2 ibl2 ibl1 ibl0 irqb mode trigger mode 0 0 0 irqb disabled, no ipl level-triggered 0 0 1 irqb enabled, ipl = 0 level-triggered 0 1 0 irqb enabled, ipl = 1 level-triggered 0 1 1 irqb enabled, ipl = 2 level-triggered 1 0 0 irqb disabled, no ipl negative-edge triggered 1 0 1 irqb enabled, ipl = 0 negative-edge triggered 1 1 0 irqb enabled, ipl = 1 negative-edge triggered 1 1 1 irqb enabled, ipl = 2 negative-edge triggered icl2 icl1 icl0 irqc mode trigger mode 0 0 0 irqc disabled, no ipl level-triggered 0 0 1 irqc enabled, ipl = 0 level-triggered 0 1 0 irqc enabled, ipl = 1 level-triggered 0 1 1 irqc enabled, ipl = 2 level-triggered 1 0 0 irqc disabled, no ipl negative-edge triggered 1 0 1 irqc enabled, ipl = 0 negative-edge triggered 1 1 0 irqc enabled, ipl = 1 negative-edge triggered 1 1 1 irqc enabled, ipl = 2 negative-edge triggered $0 idl0 idl1 idl2 idl2 idl1 idl0 irqd mode trigger mode 0 0 0 irqd disabled, no ipl level-triggered 0 0 1 irqd enabled, ipl = 0 level-triggered 0 1 0 irqd enabled, ipl = 1 level-triggered 0 1 1 irqd enabled, ipl = 2 level-triggered 1 0 0 irqd disabled, no ipl negative-edge triggered 1 0 1 irqd enabled, ipl = 0 negative-edge triggered 1 1 0 irqd enabled, ipl = 1 negative-edge triggered 1 1 1 irqd enabled, ipl = 2 negative-edge triggered sheet 4 of 8 application: date: programmer: aa1106d
d-30 DSP56602 user? manual motorola programmer? reference s0l0 hpl1 s1l1 s1l0 s0l1 interrupt priority x:$fffe reset = $0000 cpu * = reserved, program as 0 hpl0 hi08 ipl hpl1 hpl0 mode 0 0 interrupts disabled 0 1 interrupts enabled, ipl = 0 1 0 interrupts enabled, ipl = 1 1 1 interrupts enabled, ipl = 2 * 0 15 6543210 10987 14 13 12 11 * 0 * 0 register?eripheral (ipr?) * 0 * 0 * 0 tpl0 * 0 * 0 tpl1 ssi0 ipl s0l1 s0l0 mode 0 0 interrupts disabled 0 1 interrupts enabled, ipl = 0 1 0 interrupts enabled, ipl = 1 1 1 interrupts enabled, ipl = 2 timer ipl tpl1 tpl0 mode 0 0 interrupts disabled 0 1 interrupts enabled, ipl = 0 1 0 interrupts enabled, ipl = 1 1 1 interrupts enabled, ipl = 2 ssi1 ipl s1l1 s1l0 mode 0 0 interrupts disabled 0 1 interrupts enabled, ipl = 0 1 0 interrupts enabled, ipl = 1 1 1 interrupts enabled, ipl = 2 $0 sheet 5 of 8 application: date: programmer: aa1106e
programmer? reference motorola DSP56602 user? manual d-31 bus control x:$fffa reset = $001f register (bcr) cpu * = reserved, program as 0 bmw4 bmw3 bmw0 bmw1 bmw2 wait state field for external memory, binary encoded $0 * 0 15 6543210 10987 14 13 12 11 * 0 * 0 * 0 * 0 * 0 * 0 * 0 * 0 * 0 * 0 $0 DSP56602 x:$fff9 read-only register (idr) $1 0 15 6543210 10987 14 13 12 11 0001011 000 $6 0 0010 $0 $2 revision device number identification sheet 6 of 8 application: date: programmer: aa1106f
d-32 DSP56602 user? manual motorola programmer? reference patch register 0 x:$fff8 reset = (par0) par par par par par cpu par par par 15 6543210 10987 14 13 12 11 par par par par par par par par 1514131211109876543210 patch register 1 x:$fff7 reset = (par1) par par par par par par par par 15 6543210 10987 14 13 12 11 par par par par par par par par 1514131211109876543210 patch register 3 x:$fff5 reset = (par3) par par par par par par par par 15 6543210 10987 14 13 12 11 par par par par par par par par 1514131211109876543210 patch register 2 x:$fff6 reset = (par2) par par par par par par par par 15 6543210 10987 14 13 12 11 par par par par par par par par 1514131211109876543210 uninitialized uninitialized uninitialized uninitialized sheet 7 of 8 application: date: programmer: aa1106g
programmer? reference motorola DSP56602 user? manual d-33 bpmr bpmr bpmr bpmr bpmr cpu bpmr bpmr bpmr 15 6543210 10987 14 13 12 11 bpmr bpmr bpmr bpmr bpmr bpmr bpmr bpmr g15 g14 g13 g12 g11 g10 g9 g8 g7 g6 g5 g4 g3 g2 g1 g0 bpmr bpmr bpmr bpmr bpmr bpmr bpmr bpmr 15 6543210 10987 14 13 12 11 bpmr bpmr bpmr bpmr bpmr bpmr bpmr bpmr l15 l14 l13 l12 l11 l10 l9 l8 l7 l6 l5 l4 l3 l2 l1 l0 bpmr bpmr 15 6543210 10987 14 13 12 11 bpmr bpmr bpmr bpmr bpmr bpmr h7 h6 h5 h4 h3 h2 h1 h0 * 0 * 0 * 0 * 0 * 0 * 0 * 0 * 0 * = reserved, program as 0 $0 $0 bus switch program memory register low (bpmrl) x:$fff3 reset = uninitialized bus switch program memory register high (bpmrh) x:$fff2 reset = $0000 bus switch program memory register (bpmrg) x:$fff4 reset = uninitialized sheet 8 of 8 application: date: programmer: aa1106h
d-34 DSP56602 user? manual motorola programmer? reference pll control x:$fffd reset = $0000 register 0 (pctl0) mf7 mf8 mf6 mf10 mf9 pll pd2 pd1 pd0 cod df2 pen pd5 pd4 xtlr df1 pll control x:$fffc reset = $0000 register 1 (pctl1) pd6 pstp predivider factor use with pd4?d6 in pctl1 $0 * 0 15 6543210 10987 14 13 12 11 15 6543210 10987 14 13 12 11 * 0 * 0 * 0 pen description 0 pll disabled 1 pll enabled * 0 * = reserved, program as 0 xtld pd3 mf11 mf1 mf2 mf0 mf4 mf3 mf5 multiplication factor df0 pstp description 0 pll disabled during stop state 1 pll operates during stop state xtld description 0 xtal output enabled 1 xtal output disabled (xtal pin pulled high) xtlr description 0 use for external crystal frequency above 200 khz 1 use for external crystal frequency below 200 khz division factor predivider factor cod description 0 pll disabled during stop state 1 pll operates during stop state use with pd0?d3 in pctl0 sheet 1 of 1 application: date: programmer: aa1107
programmer? reference motorola DSP56602 user? manual d-35 hi08 hf3 hf2 htie hrie register (hcr) x:$ffc2 reset = $0000 read/write 15 6543210 10987 14 13 12 11 15 6543210 10987 14 13 12 11 hrdf description 0 hrx register is not full 1 hrx register is full hi08 status register (hsr) x:$ffc3 reset = $0002 hi08 control * 0 * 0 * 0 * 0 * 0 * 0 * 0 * 0 * 0 * 0 * 0 hf0 hcp ht hr df de hf1 * 0 * 0 * 0 * 0 * 0 * 0 * 0 * 0 * 0 * 0 * 0 * = reserved, program as 0 $0 $0 $0 $0 $0 htde description 0 hrx register is not empty 1 htx register is empty hcp description 0 host command interrupt is not pending (hc bit in cvr is cleared) 1 host command interrupt is pending (hc bit in cvr is set) hf0, hf1 general purpose flags. values reflect hf0, hf1 in icr on host side. htie description 0 host transmit data interrupt disabled 1 host transmit data interrupt enabled hrie description 0 host receive data interrupt disabled 1 host receive data interrupt enabled hf2, hf3 general purpose flags. values reflect hf2, hf3 in isr on host side hcie hcie description 0 host command interrupt disabled 1 host command interrupt enabled read-only sheet 1 of 5 application: date: programmer: aa1108a
d-36 DSP56602 user? manual motorola programmer? reference hrod hen hasp hdsp hrp hap hmux haen hren hc ha9 ha8 hgen hi08 port control register (hpcr) x:$ffc4 reset = $0000 hcsp hdds 15 6543210 10987 14 13 12 11 hen description 0 hi08 disabled 1 hi08 enabled hasp description 0 has pin active low 1 has pin active high hdds description 0 single strobe bus mode 1 dual strobe bus mode hcsp description 0 hcs pin active low 1 hcs pin active high hrp description 0 hreq pin (or htrq and hrrq pins) active low 1 hreq pin (or htrq and hrrq pins) active high hap description 0 hack pin active low 1 hack pin active high hren description 0 hreq /htrq and hack /hrrq used for gpio 1 hreq /htrq and hack /hrrq enabled (mode-dependent) haen description 0 hack pin configured as gpio 1 hack pin is host acknowledge input hgen description 0 disconnects pins configured for gpio 1 enables pins configured for gpio hcsen description 0 hcs /ha10 used for gpio 1 hcs /ha10 enabled ha9en description 0 ha9 used for gpio 1 ha9 enabled ha8en description 0 ha8 used for gpio 1 ha8 enabled hi08 * 0 sen en en * = reserved, program as 0 read/write hrod description 0 hreq pin not open drain 1 hreq pin is open drain hmux description 0 hi08 uses non-multiplexed bus 1 hi08 non-multiplexed bus hdsp description 0 data strobe pins active low 1 data strobe pins active high sheet 2 of 5 application: date: programmer: aa1108b
programmer? reference motorola DSP56602 user? manual d-37 hi08 hi08 data direction x:$ffc8 reset = $0000 register (hddr) dr11 dr12 dr10 dr14 dr13 dr15 dr9 dr2 dr3 dr1 dr5 dr4 dr8 dr7 dr6 dr0 15 6543210 10987 14 13 12 11 drn description 0 pin used for input 1 pin used for output read/write hi08 data x:$ffc9 reset = $0000 register (hdr) d11 d12 d10 d14 d13 d15 d9 d2 d3 d1 d5 d4 d8 d7 d6 d0 15 6543210 10987 14 13 12 11 read/write hi08 receive data x:$ffc6 reset = $0000 register (hrx) data data data data data data data data data data data data data data data data 15 6543210 10987 14 13 12 11 read-only hi08 transmit data x:$ffc7 reset = $0000 register (htx) data data data data data data data data data data data data data data data data 15 6543210 10987 14 13 12 11 write-only * = reserved, program as 0 hi08 base address x:$ffc5 reset = $0080 register (hbar) ba5 ba6 ba4 ba8 ba7 ba10 ba9 ba3 15 6543210 10987 14 13 12 11 read/write * 0 * 0 * 0 * 0 * 0 * 0 * 0 * 0 $0 $0 sheet 3 of 5 application: date: programmer: aa1108c
d-38 DSP56602 user? manual motorola programmer? reference hi08 * = reserved, program as 0 interface status reset = $06 register (isr) trdy hf2 txde hf3 hreq rxdf 6543210 7 read only * 0 * 0 hreq description 0 hreq is deasserted 1 if enabled, hreq is asserted trdy description 0 transmit fifo is empty 1 transmit fifo contains data hf2, hf3 general purpose flags, values reflect hf2, hf3 in hcr on dsp side txde description 0 htx register is full 1 htx register is empty rxdf description 0 hrx register is empty 1 hrx register is full interface control reset = $00 register (icr) hdrq hf0 treq hl hf1 init rreq 6543210 7 read/write end * 0 hf0, hf1 general purpose flags, values reflect hf0, hf1 in hsr on dsp side hlend description 0 data accessed ?ig end?first 1 data accessed ?ittle end?first treq description 0 hack or trq disabled 1 hack or trq enabled rreq description 0 hreq or rrq disabled 1 hrrq or rrq enabled hdrq description 0 hreq and hack selected 1 trq and rrq selected init see table 7-10 on page 7-25 sheet 4 of 5 application: date: programmer: aa1108d
programmer? reference motorola DSP56602 user? manual d-39 hi08 hv2 hv3 hv1 hv5 hv4 hc hv6 hv0 6543210 7 control vector reset = $32 register (cvr) read/write hv0?v6 equals vba register interrupt vector ?2 hc description 0 no host command pending 1 host command is pending iv2 iv3 iv1 iv5 iv4 iv7 iv6 iv0 6543210 7 interrupt vector reset = $0f register (ivr) read/write iv0?v7 contains interrupt vector for mc68000 family sheet 5 of 5 application: date: programmer: aa1108e
d-40 DSP56602 user? manual motorola programmer? reference * = reserved, program as 0 psr pm0 wl1 pm2 pm1 pm6 pm7 pm3 wl0 dc4 dc3 dc2 dc1 dc0 ssi 0 control register a (cra0) x:$ffb6 reset = $0000 pm5 pm4 15 6543210 1098 7 14131211 wl1 wl0 description 0 0 8 bits per word 0 1 12 bits per word 1 0 16 bits per word 1 1 (reserved) te tie re teie reie rie of1 of0 ssi 0 control register b (crb0) x:$ffb7 reset = $0000 rlie tlie 15 6543210 10987 14 13 12 11 * 0 * 0 * 0 * 0 * 0 * 0 $0 serial output flags frame rate divider bits binary encoded prescale modulus bits binary encoded reie description 0 (bit is cleared) 1 tx underrun occurred teie description 0 (bit is cleared) 1 tx underrun occurred rlie description 0 (bit is cleared) 1 tx underrun occurred tie description 0 transmit interrupt disabled 1 transmit interrupt enabled re description 0 receive disabled 1 receive enabled te description 0 transmit disabled 1 transmit enabled tlie description 0 (bit is cleared) 1 tx underrun occurred rie description 0 receive interrupt disabled 1 receive interrupt enabled read/write read/write ssi0 sheet 1 of 4 application: date: programmer: aa1109a
programmer? reference motorola DSP56602 user? manual d-41 ssi0 scd2 ckp sckd fsr fsp shfd mod syn ssi 0 control register c (crc0) x:$ffb8 reset = $0000 fsl1 fsl0 15 6543210 10987 14 13 12 11 * 0 * 0 * 0 * 0 $0 scd1 scd0 scd0 description 0 sc0 pin is input 1 sc0 pin is output mod description 0 normal mode selected 1 network mode selected scd1 description 0 sc1 pin is input 1 sc1 pin is output scd2 description 0 sc2 pin is input 1 sc2 pin is output sckd description 0 external clock source 1 internal clock source ckp description 0 data clocked out on rising edge of tx clock, latched in on falling edge of rx clock 1 data clocked out on falling edge of tx clock, latched in on rising edge of rx clock * = reserved, program as 0 syn description 0 asynchronous mode selected 1 synchronous mode selected shfd description 0 data shifted out msb first 1 data shifted out lsb first fsl1 fsl0 description 0 0 wl bit clock for both tx and rx 0 1 one-bit clock for tx wl bit clock for rx 1 0 one-bit clock for both tx and rx 1 1 wl bit clock for tx one-bit clock for rx fsr description 0 frame synch occurs with first bit of current word 1 frame synch occurs with last bit of previous word fsp description 0 positive frame synch 1 negative frame synch sheet 2 of 4 application: date: programmer: aa1109b
d-42 DSP56602 user? manual motorola programmer? reference * = reserved, program as 0 ssi 0 transmit register (tx0) x:$ffbc write-only high byte 15 6543210 10987 14 13 12 11 low byte ssi 0 receive register (rx0) x:$ffba read-only high byte 15 6543210 10987 14 13 12 11 low byte ssi0 ssi 0 time slot register (tsr0) x:$ffbb write-only dummy register, written during inactive time slots 15 6543210 10987 14 13 12 11 tue description 0 (bit is cleared) 1 tx underrun occurred rdf tde roe tue rfs tfs if1 if0 * 0 15 6543210 10987 14 13 12 11 * = reserved, program as 0 * 0 * 0 * 0 * 0 * 0 * 0 * 0 $0 $0 ssi 0 status register (ssisr0) x:$ffb9 reset = $0040 rdf description 0 (bit is cleared) 1 rx data register has data tde description 0 (bit is cleared) 1 tx data register empty roe description 0 (bit is cleared) 1 rx overrun occurred tfs description 0 no frame sync 1 tx frame sync occurred rfs description 0 no frame sync 1 rx frame sync occurred serial input flags sheet 3 of 4 application: date: programmer: aa1109c
programmer? reference motorola DSP56602 user? manual d-43 ssi0 * = reserved, program as 0 ssi 0 port c control x:$ffbf reset = $0000 register (pcrc) pc2 pc3 pc1 pc5 pc4 pen pc0 15 6543210 10987 14 13 12 11 pcn description 0 pin is gpio pin 1 pin is ssi pin ssi 0 port c x:$ffbe reset = $0000 register (prrc) pdc2 pdc3 pdc1 pdc5 pdc4 pdc0 pd2 pd3 pd1 pd5 pd4 pd0 15 6543210 10987 14 13 12 11 15 6543210 10987 14 13 12 11 data direction ssi 0 port c data x:$ffbd reset = $0000 register (pdrc) read/write * 0 * 0 * 0 * 0 $0 * 0 * 0 * 0 * 0 $0 * 0 pen description 0 ssi pins tri-stated 1 ssi pins enabled pdn description 0 pin is input 1 pin is output * 0 * 0 * 0 * 0 $0 * 0 * 0 * 0 * 0 $0 * 0 * 0 read/write * 0 * 0 * 0 * 0 $0 * 0 * 0 * 0 * 0 $0 * 0 * 0 read/write sheet 4 of 4 application: date: programmer: aa1109d
d-44 DSP56602 user? manual motorola programmer? reference * = reserved, program as 0 psr pm0 wl1 pm2 pm1 pm6 pm7 pm3 wl0 dc4 dc3 dc2 dc1 dc0 ssi 1 control register a (cra1) x:$ffa6 reset = $0000 pm5 pm4 15 6543210 1098 7 14131211 ssi1 wl1 wl0 description 0 0 8 bits per word 0 1 12 bits per word 1 0 16 bits per word 1 1 (reserved) te tie re teie reie rie of1 of0 ssi 1 control register b (crb1) x:$ffa7 reset = $0000 rlie tlie 15 6543210 10987 14 13 12 11 * 0 * 0 * 0 * 0 * 0 * 0 $0 serial output flags frame rate divider bits binary encoded prescale modulus bits binary encoded reie description 0 (bit is cleared) 1 tx underrun occurred teie description 0 (bit is cleared) 1 tx underrun occurred rlie description 0 (bit is cleared) 1 tx underrun occurred tie description 0 transmit interrupt disabled 1 transmit interrupt enabled re description 0 receive disabled 1 receive enabled te description 0 transmit disabled 1 transmit enabled tlie description 0 (bit is cleared) 1 tx underrun occurred rie description 0 receive interrupt disabled 1 receive interrupt enabled read/write read/write sheet 1 of 4 application: date: programmer: aa1110a
programmer? reference motorola DSP56602 user? manual d-45 ssi1 scd2 ckp sckd fsr fsp shfd mod syn ssi 1 control register c (crc1) x:$ffa8 reset = $0000 fsl1 fsl0 15 6543210 10987 14 13 12 11 * 0 * 0 * 0 * 0 $0 scd1 scd0 scd0 description 0 sc0 pin is input 1 sc0 pin is output mod description 0 normal mode selected 1 network mode selected scd1 description 0 sc1 pin is input 1 sc1 pin is output scd2 description 0 sc2 pin is input 1 sc2 pin is output sckd description 0 external clock source 1 internal clock source ckp description 0 data clocked out on rising edge of tx clock, latched in on falling edge of rx clock 1 data clocked out on falling edge of tx clock, latched in on rising edge of rx clock * = reserved, program as 0 syn description 0 asynchronous mode selected 1 synchronous mode selected shfd description 0 data shifted out msb first 1 data shifted out lsb first fsr description 0 frame synch occurs with first bit of current word 1 frame synch occurs with last bit of previous word fsp description 0 positive frame synch 1 negative frame synch fsl1 fsl0 description 0 0 wl bit clock for both tx and rx 0 1 one-bit clock for tx wl bit clock for rx 1 0 one-bit clock for both tx and rx 1 1 wl bit clock for tx one-bit clock for rx sheet 2 of 4 application: date: programmer: aa1110b
d-46 DSP56602 user? manual motorola programmer? reference * = reserved, program as 0 ssi 1 transmit register (tx1) x:$ffac write-only high byte 15 6543210 10987 14 13 12 11 low byte ssi 1 receive register (rx1) x:$ffaa read-only high byte 15 6543210 10987 14 13 12 11 low byte ssi1 ssi 1 time slot register (tsr1) x:$ffab write-only dummy register, written during inactive time slots 15 6543210 10987 14 13 12 11 tue description 0 (bit is cleared) 1 tx underrun occurred rdf tde roe tue rfs tfs if1 if0 * 0 15 6543210 10987 14 13 12 11 * = reserved, program as 0 * 0 * 0 * 0 * 0 * 0 * 0 * 0 $0 $0 ssi 1 status register (ssisr1) x:$ffa9 reset = $0040 rdf description 0 (bit is cleared) 1 rx data register has data tde description 0 (bit is cleared) 1 tx data register empty roe description 0 (bit is cleared) 1 rx overrun occurred tfs description 0 no frame sync 1 tx frame sync occurred rfs description 0 no frame sync 1 rx frame sync occurred serial input flags sheet 3 of 4 application: date: programmer: aa1110c
programmer? reference motorola DSP56602 user? manual d-47 ssi1 * = reserved, program as 0 ssi 1 port d control x:$ffaf reset = $0000 register (pcrd) pc2 pc3 pc1 pc5 pc4 pen pc0 15 6543210 10987 14 13 12 11 pcn description 0 pin is gpio pin 1 pin is ssi pin ssi 1 port d x:$ffae reset = $0000 register (prrd) pdc2 pdc3 pdc1 pdc5 pdc4 pdc0 pd2 pd3 pd1 pd5 pd4 pd0 15 6543210 10987 14 13 12 11 15 6543210 10987 14 13 12 11 data direction ssi 1 port d data x:$ffad reset = $0000 register (pdrd) read/write * 0 * 0 * 0 * 0 $0 * 0 * 0 * 0 * 0 $0 * 0 pen description 0 ssi pins tri-stated 1 ssi pins enabled pdn description 0 pin is input 1 pin is output * 0 * 0 * 0 * 0 $0 * 0 * 0 * 0 * 0 $0 * 0 * 0 read/write * 0 * 0 * 0 * 0 $0 * 0 * 0 * 0 * 0 $0 * 0 * 0 read/write sheet 4 of 4 application: date: programmer: aa1110d
d-48 DSP56602 user? manual motorola programmer? reference gpio * = reserved, program as 0 gpio port e control x:$ff9f reset = $0000 register (pcre) pc2 pc1 pc0 15 6543210 10987 14 13 12 11 x:$ff9e reset = $0000 register (prre) pdc2 pdc1 pdc0 pd2 pd1 pd0 15 6543210 10987 14 13 12 11 15 6543210 10987 14 13 12 11 gpio port e direction gpio port e data x:$ff9d reset = $0007 register (pdre) read/write * 0 * 0 * 0 * 0 $0 * 0 * 0 * 0 * 0 $0 pcn pdcn port pin function 0 0 gpio input 0 1 gpio output 1 0 tri-stated 1 1 gpio output, open-drain * 0 * 0 * 0 * 0 $0 * 0 * 0 * 0 * 0 $0 read/write * 0 * 0 * 0 * 0 $0 * 0 * 0 * 0 * 0 $0 read/write * 0 * 0 * 0 * 0 $0 * 0 * 0 * 0 * 0 * 0 $0 * 0 * 0 * 0 * 0 * 0 $0 * 0 sheet 1 of 1 application: date: programmer: aa1111
programmer? reference motorola DSP56602 user? manual d-49 timers * = reserved, program as 0 timer prescaler load register reset = $0000 read/write 15 6543210 10987 14 13 12 11 15 6543210 10987 14 13 12 11 x:$ff83 (tplr) ps1 ps0 pl13 pl12 pl11 pl10 pl9 pl8 pl7 pl6 pl5 pl4 pl3 pl2 pl1 pl0 pc13 pc12 pc11 pc10 pc9 pc8 pc7 pc6 pc5 pc4 pc3 pc2 pc1 pc0 * 0 * 0 timer prescaler count register reset = uninitialized read-only x:$ff82 (tpcr) ps1 ps0 prescaler clock source 0 0 internal clock ?2 0 1 tio0 1 0 tio1 1 1 tio2 pc0?c13 prescaler count value pl0?l13 prescaler load value sheet 1 of 4 application: date: programmer: aa1112a
d-50 DSP56602 user? manual motorola programmer? reference timer0 * = reserved, program as 0 te description 0 timer disabled 1 timer enabled toie description 0 timer overflow interrupt disabled 1 timer overflow interrupt enabled inv description 0 timer increments on rising transitions 1 timer increments on falling transitions see inverter bit (inv)?it 8 on page 9-11 for more information. timer 0 control/ x:$ff8f reset = $0000 (tcsr0) tc3 tc2 te tcie toie tc0 inv di do pce trm dir status register 15 6543210 10987 14 13 12 11 read/write tof tcf tc1 * 0 tcie description 0 timer compare interrupt disabled 1 timer compare interrupt enabled trm description 0 timer is free-running 1 timer reloads when tcr value is reached see data input bit (di)?it 11 on page 9-11 tof description 0 (bit is cleared) 1 timer overflow detected tcf description 0 (bit is cleared) 1 timer has reached value in tcr pce description 0 prescaler disabled 1 prescaler enabled dir description 0 tio pin is input 1 tio pin is output see data output bit (do)?it 12 on page 9-12 timer 0 load x:$ff8e register (tlr0) reset = uninitialized write-only 15 6543210 10987 14 13 12 11 timer 0 compare x:$ff8d register (tcpr0) 15 6543210 10987 14 13 12 11 reset = uninitialized read/write timer 0 count x:$ff8c register (tcr0) 15 6543210 10987 14 13 12 11 reset = $0000 read-only timer mode control bits see table 9-2 on page 9-10 sheet 2 of 4 application: date: programmer: aa1112b
programmer? reference motorola DSP56602 user? manual d-51 timer1 te description 0 timer disabled 1 timer enabled toie description 0 timer overflow interrupt disabled 1 timer overflow interrupt enabled inv description 0 timer increments on rising transitions 1 timer increments on falling transitions see inverter bit (inv)?it 8 on page 9-11 for more information. timer 1 control/ x:$ff8b reset = $0800 (tcsr1) tc3 tc2 te tcie toie tc0 inv di do pce trm dir status register 15 6543210 10987 14 13 12 11 read/write tof tcf tc1 * 0 tcie description 0 timer compare interrupt disabled 1 timer compare interrupt enabled trm description 0 timer is free-running 1 timer reloads when tcr value is reached see data input bit (di)?it 11 on page 9-11 tof description 0 (bit is cleared) 1 timer overflow detected tcf description 0 (bit is cleared) 1 timer has reached value in tcr pce description 0 prescaler disabled 1 prescaler enabled dir description 0 tio pin is input 1 tio pin is output see data output bit (do)?it 12 on page 9-12 * = reserved, program as 0 timer 1 load x:$ff8a register (tlr1) reset = uninitialized write-only 15 6543210 10987 14 13 12 11 timer 1 compare x:$ff89 register (tcpr1) 15 6543210 10987 14 13 12 11 reset = uninitialized read/write timer 1 count x:$ff88 register (tcr1) 15 6543210 10987 14 13 12 11 reset = $0000 read-only timer mode control bits see table 9-2 on page 9-10 sheet 3 of 4 application: date: programmer: aa1112c
d-52 DSP56602 user? manual motorola programmer? reference timer2 te description 0 timer disabled 1 timer enabled toie description 0 timer overflow interrupt disabled 1 timer overflow interrupt enabled inv description 0 timer increments on rising transitions 1 timer increments on falling transitions see inverter bit (inv)?it 8 on page 9-11 for more information. timer 2 control/ x:$ff87 reset = $0800 (tcsr2) tc3 tc2 te tcie toie tc0 inv di do pce trm dir status register 15 6543210 10987 14 13 12 11 read/write tof tcf tc1 * 0 tcie description 0 timer compare interrupt disabled 1 timer compare interrupt enabled trm description 0 timer is free-running 1 timer reloads when tcr value is reached see data input bit (di)?it 11 on page 9-11 tof description 0 (bit is cleared) 1 timer overflow detected tcf description 0 (bit is cleared) 1 timer has reached value in tcr pce description 0 prescaler disabled 1 prescaler enabled dir description 0 tio pin is input 1 tio pin is output see data output bit (do)?it 12 on page 9-12 * = reserved, program as 0 timer 2 load x:$ff86 register (tlr2) reset = uninitialized write-only 15 6543210 10987 14 13 12 11 timer 2 compare x:$ff85 register (tcpr2) 15 6543210 10987 14 13 12 11 reset = uninitialized read/write timer 2 count x:$ff84 register (tcr2) 15 6543210 10987 14 13 12 11 reset = $0000 read-only timer mode control bits see table 9-2 on page 9-10 sheet 4 of 4 application: date: programmer: aa1112d
motorola DSP56602 user? manual index-1 index a a0?15 signals 2-10 adder modulo 1-8 offset 1-8 reverse-carry 1-8 address bus ground signal (gnd a ) 2-6 address bus power signal (v cca ) 2-5 address bus signals (a0?15) 2-10 address bus?0?15 5-3 address generation unit 1-8 address trace enable bit (ate) 4-6 address trace signal (at ) 2-11 , 5-4 address tracing (at) mode 5-10 agu 1-8 asynchronous/synchronous bit (syn) 8-14 at mode 5-10 at signal 2-11 , 5-4 ate bit 4-6 b ba3?a10 bits 7-17 base address bits (ba3?a10) 7-17 bcr register 4-8 , 5-7 bits 0??xpansion bus memory wait bits (bmw0?mw4) 5-7 reserved bits?its 5?5 5-8 bmpr register 5-8 bmw0?mw4 bits 5-7 boundary scan register (bsr) 11-7 bpmr register 16-bit access 5-9 24-bit access 5-9 mapping 5-8 typical usage 5-9 breakpoint 0 and 1 event bits (bt0?t1) 10-14 breakpoint 0 condition code select bits (cc00?c01) 10-13 breakpoint 0 read/write select bits (rw00?w01) 10-12 breakpoint 1 condition code select bits (cc10?c11) 10-14 breakpoint 1 read/write select bits (rw10?w11) 10-13 bsr bit definitions 11-13 bsr register 11-7 bt0?t1 bits 10-14 bus control ground signal (gnd c ) 2-6 bus control power signal (v ccc ) 2-5 bus control register (bcr) 4-8 , 5-7 bus switch program memory register (bpmr) 5-8 buses internal 1-11 bypass instruction 11-12 c cc00?c01 bits 10-13 cc10?c11 bits 10-14 ccr register 4-7 chip operating mode bits (md,mc, mb, and ma) 4-4 chip operating modes 4-9 ckp bit 8-15 clamp instruction 11-10 clkout signal 2-7 clock output disable bit (cod) 4-19 clock output signal (clkout) 2-7 clock polarity bit (ckp) 8-15 clock signals 2-7 clock source direction bit (sckd) 8-15 cod bit 4-19 command vector register (cvr) 7-25 condition code register (ccr) 4-7 configuration gpio 6-3 core status bits (os0?s1) 10-9 cra register 8-7 bits 0??rescale modulus select bits (pm0?m7) 8-8 bits 8?2?rame rate divider control bits (dc4?c0) 8-8 bits 13?4?ord length control bits (wl0?l1) 8-8 bit 15?rescaler range bit (psr) 8-9 crb register bit 0?erial output flag 0 bit (of0) 8-10 bit 1?erial output flag 1 bit (of1) 8-10 bit 8?ransmit enable bit (te) 8-11 bit 9?eceive enable bit (re) 8-12 bit 10?ransmit interrupt enable bit (tie) 8-12 bit 11?eceive interrupt enable bit (rie) 8-12 bit 12?ransmit last slot interrupt enable bit (tlie) 8-13 bit 13?eceive last slot interrupt enable bit (rlie) 8-13 bit 14?ransmit exception interrupt enable bit (teie) 8-13
d index-2 DSP56602 user? manual motorola bit 15?eceive exception interrupt enable bit (reie) 8-13 reserved bits?its 2? 8-10 crc register bit 0?synchronous/synchronous bit (syn) 8-14 bit 1?si mode select bit (mod) 8-14 bit 2?erial control 0 direction bit (scd0) 8-14 bit 3?erial control 1 direction bit (scd1) 8-14 bit 4?erial control 2 direction bit (scd2) 8-15 bit 5?lock source direction bit (sckd) 8-15 bit 6?lock polarity bit (ckp) 8-15 bit 7?hift direction bit (shfd) 8-15 bits 12?3?rame sync length bits (fsl1?sl0) 8-15 bit 14?rame sync relative timing bit (fsr) 8-16 bit 15?rame sync polarity bit (fsp) 8-16 reserved bits?its 8?1 8-15 crystal output signal (xtal) 2-7 crystal range bit (xtlr) 4-19 cvr register 7-25 bits 0??ost vector bits (hv0?v6) 7-25 bit 7?ost command bit (hc) 7-26 d d0?23 signals 2-10 data alu 1-7 data bus ground signal (gnd d ) 2-6 data bus power signal (v ccd ) 2-5 data bus power signal (v cch ) 2-5 data bus signals (a0?15) 2-10 data bus?0?23 5-3 data input bit (di) 9-11 data output bit (do) 9-12 dc4?c0 bits 8-8 de signal 2-26 , 10-4 debug event signal (de signal) 2-26 , 10-4 debug mode in once module 10-16 debug_request instruction 11-11 executing during stop state 10-17 executing during wait state 10-17 executing in once module 10-17 device identification register (idr) 4-8 df2?f0 bits 4-18 di bit 9-11 dir bit 9-11 direction bit (dir) 9-11 division factor bits (df2?f0) 4-18 do bit 9-12 double host request bit (hdrq) 7-24 e ebd bit 4-5 en bit 4-6 enable_once instruction 11-11 eov bit 4-6 eun bit 4-5 ex bit 10-7 exit command bit (ex) 10-7 expanded mode (mode 0) 4-10 expansion bus memory wait bits (bmw0?mw4) 5-7 expansion port signals 2-10 expansion port, port a pins 2-10 extal signal 2-7 extended stack enable bit (en) 4-6 extended stack overflow bit (eov) 4-6 extended stack underflow bit (eun) 4-5 extended stack wrap bit (wr) 4-6 external bus disable bit (ebd) 4-5 external clock/crystal input signal (extal) 2-7 extest instruction 11-9 f frame rate divider control bits (dc4?c0) 8-8 frame sync length bits (fsl1?sl0) 8-15 frame sync polarity bit (fsp) 8-16 frame sync relative timing bit (fsr) 8-16 fsl1?sl0 bits 8-15 fsp bit 8-16 fsr bit 8-16 g general purpose i/o (gpio) port 6-3 general purpose i/o 0 signal (gpi00) 2-24 general purpose i/o 1 signal (gpi01) 2-24 general purpose i/o 2 signal (gpi02) 2-24 general purpose i/o signals 2-24 global data bus 1-11 gnd a signal 2-6
h motorola DSP56602 user? manual index-3 gnd c signal 2-6 gnd d signal 2-6 gnd h signal 2-6 gnd p signal 2-6 gnd q signal 2-6 gnd s signal 2-6 go command bit (go) 10-7 gpi00 signal 2-24 gpi01 signal 2-24 gpi02 signal 2-24 gpio 1-13 configuration 6-3 in hi08 7-30 gpio control register (pcre) 6-5 gpio data register (pdre) 6-6 gpio signals 2-24 ground signals 2-6 h ha0 signal 2-13 ha1 signal 2-14 ha10 signal 2-16 ha2 signal 2-14 ha8 signal 2-14 ha8en bit 7-12 ha9 signal 2-14 ha9en bit 7-12 hack signal 2-17 had0?ad7 signals 2-13 haen bit 7-13 hap bit 7-16 hardware reset signal (reset ) 2-8 has signal 2-13 hasp bit 7-14 hbar register 7-17 bits 0??ase address bits (ba3?a10) 7-17 reserved bits?its 5?5 7-17 hc bit 7-26 hcie bit 7-9 hcp bit 7-11 hcr register bit 0?ost receive interrupt enable bit (hrie) 7-9 bit 1?ost transmit interrupt enable bit (htie) 7-9 bit 2?ost command interrupt enable bit (hcie) 7-9 bits 3, 4?ost flag 2 and 3 bits (hf2, hf3) 7-10 reserved bits?its 5?5 7-10 hcs signal 2-16 hcsen bit 7-13 hcsp bit 7-15 hd0?d7 signals 2-13 hddr register 7-16 hdds bit 7-14 hdr register 7-16 hdrq bit 7-24 hds signal 2-15 hdsp bit 7-14 hen bit 7-13 hf0 bit 7-11 , 7-24 hf1 bit 7-11 , 7-24 hf2 bit 7-10 , 7-27 hf3 bit 7-10 , 7-27 hgen bit 7-12 hi08 data transfer 7-31 polling 7-31 servicing interrupts 7-32 hi08 base address register (hbar) 7-17 hi08 control register (hcr 7-8 hi08 data direction register (hddr) 7-16 hi08 data register (hdr) 7-16 hi08 receive data register (hrx) 7-18 hi08 signals 2-13 hi08 status register (hsr) 7-10 hi08 transmit data register (htx) 7-18 hi-z instruction 11-11 hlend bit 7-24 hmux bit 7-14 host acknowledge enable bit (haen) 7-13 host acknowledge polarity bit (hap) 7-16 host acknowledge signal (hack ) 2-17 host address 8 signal (ha8) 2-14 host address 9 signal (ha8) 2-14 host address bus signals (had0?ad7) 2-13 host address input 0 signal (ha0) 2-13 host address input 1 signal (ha01) 2-14 host address input 2 signal (ha2) 2-14 host address input 10 signal (ha10) 2-16 host address line 8 enable bit (ha8en) 7-12 host address line 9 enable bit (ha9en) 7-12 host address strobe polarity bit (hasp) 7-14 host address strobe signal (has ) 2-13 host chip select enable bit (hcsen) 7-13 host chip select polarity bit (hcsp) 7-15 host chip select signal (hcs ) 2-16 host command bit (hc) 7-26 host command interrupt enable bit (hcie) 7-9 host command pending bit (hcp) 7-11
i index-4 DSP56602 user? manual motorola host data bus signals (hd0?d7) 2-13 host data strobe polarity bit (hdsp) 7-14 host data strobe signal (hds ) 2-15 host dual data strobe bit (hdds) 7-14 host enable bit (hen) 7-13 host flag 0 bit (hf0) 7-11 , 7-24 host flag 1 bit (hf1) 7-11 , 7-24 host flag 2 bit (hf2) 7-10 , 7-27 host flag 3 bit (hf3) 7-10 , 7-27 host gpio port enable bit (hgen) 7-12 host ground signal (gnd h ) 2-6 host interface (hi08) 7-3 host interface (hi08)?i08 1-13 host interface signals (hi08) 2-13 host little endian bit (hlend) 7-24 host multiplexed bus bit (hmux) 7-14 host port control register (hpcr) 7-12 host port usage 2-12 host read data signal (hrd ) 2-15 host read/write signal (hrw) 2-15 host receive data full bit (hrdf) 7-10 host receive interrupt enable bit (hrie) 7-9 host request enable bit (hren) 7-13 host request open drain bit (hrod) 7-13 host request polarity bit (hrp) 7-15 host request signal (hreq ) 2-16 host transmit data empty bit (htde) 7-11 host transmit interrupt enable bit (htie) 7-9 host vector bits (hv0?v6) 7-25 host write enable strobe signal (hwr ) 2-15 hpcr register bit 0?ost gpio port enable bit (hgen) 7-12 bit 1?ost address line 8 bit (ha8en) 7-12 bit 2?ost address line 9 bit (ha9en) 7-12 bit 3?ost chip select enable bit (hcsen) 7-13 bit 4?ost request enable bit (hren) 7-13 bit 5?ost acknowledge enable bit (haen) 7-13 bit 6?ost enable bit (hen) 7-13 bit 8?ost request open drain bit (hrod) 7-13 bit 9?ost data strobe polarity bit (hdsp) 7-14 bit 10?ost address strobe polarity bit (hasp) 7-14 bit 11?ost multiplexed bus bit (hmux) 7-14 bit 12?ost dual data strobe bit (hdds) 7-14 bit 13?ost chip select polarity bit (hcsp) 7-15 bit 14?ost request polarity bit (hrp) 7-15 bit 15?ost acknowledge polarity bit (hap) 7-16 reserved bit?it 7 7-13 hrd signal 2-15 hrdf bit 7-10 hren bit 7-13 hreq bit 7-27 hreq signal 2-16 hrie bit 7-9 hrod bit 7-13 hrp bit 7-15 hrrq signal 2-17 hrw signal 2-15 hrx register 7-18 hsr register bit 0?ost receive data full bit (hrdf) 7-10 bit 1?ost transmit data empty bit (htde) 7-11 bit 2?ost command pending bit (hcp) 7-11 bits 3, 4?ost flag 0 and 1 bits (hf0, hf1) 7-11 reserved bits?its 5?5 7-11 htde bit 7-11 htie bit 7-9 htrq signal 2-16 htx register 7-18 hv0?v6 bits 7-25 hwr signal 2-15 i icr register 7-22 bit 0?eceive request enable bit (rreq) 7-23 bit 1?ransmit request enable bit (treq) 7-23 bit 2?ouble host request bit (hdrq) 7-24 bit 3?ost flag 0 bit (hf0) 7-24 bit 4?ost flag 1 bit (hf1) 7-24 bit 5?ost little endian bit (hlend) 7-24 bit 7?nitialize bit (init) 7-24 reserved bit?it 6 7-25 idcode instruction 11-9 idr register 4-8 if0 bit 8-17 if1 bit 8-17 ime bit 10-8
j motorola DSP56602 user? manual index-5 init bit 7-24 initialize bit (init) 7-24 input and output signals 2-3 interface control register (icr) 7-22 interface status register (isr) 7-26 internal buses 1-11 interrupt 10-8 interrupt and mode control pins 2-8 interrupt control signals 2-8 interrupt mode enable bit (ime) 10-8 interrupt priority levels 4-13 interrupt priority register?ore (ipr-c) 4-13 interrupt priority register?eripheral (ipr-p) 4-13 interrupt starting address 4-11 interrupt vector register (ivr) 7-28 inv bit 9-11 inverter bit (inv) 9-11 ipr-c register 4-13 ipr-p register 4-13 isr host request bit (hreq) 7-27 isr register 7-26 bit 0?eceive data register full bit (rxdf) 7-26 bit 1?ransmit data register empty bit (txde) 7-27 bit 2?ransmitter ready bit (trdy) 7-27 bit 3?ost flag 2 bit (hf2) 7-27 bit 4?ost flag 3 bit (hf3) 7-27 bit 7?sr host request bit (hreq) 7-27 reserved bits?its 5, 6 7-27 ivr register 7-28 j joint test action group (jtag) 11-3 jtag 1-10 jtag instructions bypass instruction 11-12 clamp instruction 11-10 debug_request instruction 11-11 enable_once instruction 11-11 extest instruction 11-9 hi-z instruction 11-11 idcode instruction 11-9 sample/preload instruction 11-9 jtag/once interface signals 2-26 debug event signal (de signal) 2-26 , 10-4 test clock signal (tck) 2-26 test data input signal (tdi) 2-26 test data output signal (tdo) 2-26 test mode select signal (tms) 2-26 test reset signal (trst ) 2-26 l la register 1-9 lc register 1-9 loop address register (la) 1-9 loop counter register (lc) 1-9 m mac 1-7 mbo bit 10-9 mbs0?bs1 bits 10-12 mcs signal 2-10 , 5-3 md,mc, mb, and ma bits 4-4 memory on-chip 1-11 memory breakpoint occurrence bit (mbo) 10-9 memory breakpoint select bits (mbs0?bs1) 10-12 memory breakpoints enabling 10-18 memory chip select signal (mcs ) 2-10 , 5-3 memory map description 3-3 memory-mapped i/o registers 3-5 mf0?f11 bits 4-17 mod bit 8-14 moda/irqa signal 2-8 modb/irqb signal 2-9 modc/irqc signal 2-9 modd/irqd signal 2-10 mode control signals 2-8 mode register (mr) 4-7 mode select a/external interrupt request a signal (moda/irqa ) 2-8 mode select b/external interrupt request b signal (moda/irqb ) 2-9 mode select c/external interrupt request c signal (modc/irqc ) 2-9 mode select d/external interrupt request d signal (modd/irqd ) 2-10 modulo adder 1-8 mr register 4-7 multiplication factor bits (mf0?f11) 4-17 multiplier-accumulator 1-7 n normal mode 4-10
o index-6 DSP56602 user? manual motorola o obcr register 10-12 bits 0??emory breakpoint select bits (mbs0?bs1) 10-12 bits 2??reakpoint 0 read/write select bits (rw00?w01) 10-12 bits 4??reakpoint 0 condition code select bits (cc00?c01) 10-13 bits 6??reakpoint 1 read/write select bits (rw10?w11) 10-13 bits 8??reakpoint 1 condition code select bits (cc10?c11) 10-14 bits 10?1?reakpoint 0 and 1 event select bits (bt0?t1) 10-14 reserved bits?its 12?5 10-14 ocr register bits 0??egister select bits (rs0?s4) 10-5 bit 5?xit command bit (ex) 10-7 bit 6?o command bit (go) 10-7 bit 7?ead/write command bit (r/w ) 10-7 odec 10-8 of0 bit 8-10 of1 bit 8-10 offset adder 1-8 ogdbr register 5-10 , 10-20 omac0 comparator 10-11 omac1 comparator 10-11 omal register 10-11 ombc counter 10-14 omlr0 register 10-11 omlr1 register 10-11 omr register 1-9 bits 0??hip operating mode bits (md,mc, mb, and ma) 4-4 bit 4?xternal bus disable bit (ebd) 4-5 bit 5?c relative disable bit (pcd) 4-5 bit 6?top delay bit (sd) 4-5 bit 8?y select bit (xy) 4-5 bit 9?xtended stack underflow bit (eun) 4-5 bit 10?xtended stack overflow bit (eov) 4-6 bit 11?xtended stack wrap bit (wr) 4-6 bit 12?xtended stack enable bit (en) 4-6 bit 15?ddress trace enable bit (ate) 4-6 reserved bits?it 7, 13, 14 4-6 once breakpoint control register (obcr) 10-12 once command register (ocr) 10-5 once commands 10-23 once controller 10-4 once decoder (odec) 10-8 once gdb register (ogdbr) 10-20 once global data bus register (ogdbr) 5-10 once memory address comparator 0 (omac0) 10-11 once memory address comparator 1 (omac1) 10-11 once memory address latch register (omal) 10-11 once memory breakpoint counter (ombc) 10-14 once memory limit register 0 (omlr0) 10-11 once memory limit register 1 (omlr1) 10-11 once module 1-11 , 10-3 checking for debug mode 10-24 displaying a specified register 10-26 displaying x data memory 10-27 interaction with jtag port 10-29 polling the jtag instruction shift register 10-25 reading the trace buffer 10-25 returning to normal mode 10-28 saving pipeline information 10-25 once pab register for decode register (opabdr) 10-20 once pab register for execute (opabex) 10-21 once pab register for fetch register (opabfr) 10-20 once pil register (opilr) 10-19 once program data bus register (opdbr) 10-19 once status and control register (oscr) 10-8 once trace counter (otc) 10-15 once trace logic 10-15 once/jtag interface pins 2-26 on-chip emulation module 1-11 , 10-3 on-chip memory 1-11 on-chip program memory 3-3 on-chip x data memory 3-4 on-chip y data memory 3-4 opabdr register 10-20 opabex register 10-21 opabfr register 10-20 opdbr register 10-19 operating mode register (omr) 1-9 , 4-4 opilr register 10-19 os0?s1 bits 10-9 oscr register 10-8 bit 0?race mode enable bit (tme) 10-8 bit 1?nterrupt mode enable bit (ime) 10-8
p motorola DSP56602 user? manual index-7 bit 2?oftware debug occurrence bit (swo) 10-8 bit 3?emory breakpoint occurrence bit (mbo) 10-9 bit 4?race occurrence bit (to) 10-9 bit 5?eserved bit 10-9 bits 6??ore status bits (os0?s1) 10-9 reserved bits?its 8?3 10-9 otc counter 10-15 p pab 1-12 pag 1-9 par register 4-3 patch address register (par) 4-3 pb0?b7 signals 2-13 pb10 signal 2-14 pb11 signal 2-15 pb12 signal 2-15 pb13 signal 2-16 pb14 signal 2-16 pb15 signal 2-17 pb8 signal 2-13 pb9 signal 2-14 pc bits 6-5 pc register 1-9 pc relative disable bit (pcd) 4-5 pc0 signal 2-18 pc0?c13 bits 9-8 pc0?c5 bits 8-20 pc1 signal 2-18 pc2 signal 2-19 pc3 signal 2-19 pc4 signal 2-20 pc5 signal 2-20 pcap signal 2-7 pcd bit 4-5 pce bit 9-12 pcrc register 8-20 bits 0??ort control bits (pc0?c5) 8-20 bit 7?ort enable bit (pen) 8-21 reserved bits?it 6, bits 8?5 8-21 pcrd register 8-20 bits 0??ort control bits (pc0?c5) 8-20 bit 7?ort enable bit (pen) 8-21 reserved bits?it 6, bits 8?5 8-21 pcre register 6-5 bits 0??ort control bits (pc) 6-5 reserved bits?its 4?5 6-5 pctl0 register bits 0?1?ultiplication factor bits (mf0?f11) 4-17 bits 12?5?redivider factor bits (pd0?d3) 4-17 pctl1 register 4-18 bits 0??ivision factor bits (df2?f0) 4-18 bit 3?rystal range (xtlr) bit 4-19 bit 4?tal disable bit (xtld) 4-19 bit 5?top processing state bit (pstp) 4-19 bit 6?ll enable bit (pen) 4-19 bit 7?lock output disable bit (cod) 4-19 bits 9?1?redivider factor bits (pd4?d6) 4-20 reserved bits?it 8, bits 12?5 4-20 pcu 1-8 pd bits 6-6 pd0 signal 2-21 pd0?d3 bits 4-17 pd1 signal 2-21 pd2 signal 2-22 pd3 signal 2-22 pd4 signal 2-23 pd4?d6 bits 4-20 pd5 signal 2-23 pdb 1-11 pdc 1-9 pdc bits 6-5 pdrc register 8-22 pdrd register 8-22 pdre register 6-6 bits 0??ort data bits (pd) 6-6 pen bit 4-19 , 8-21 phase lock loop (pll) 1-10 , 4-16 pic 1-9 pinit/nmi signal 2-7 pl0?l13 bits 9-7 pll 1-10 pll capacitor signal (pcap) 2-7 pll control register 0 (pctl0) 4-17 pll control register 1 (pctl1) 4-18 pll enable bit (pen) 4-19 pll ground signal (gnd p ) 2-6 pll initial /non-maskable interrupt signal (pinit/nmi ) 2-7 pll power signal (v ccp ) 2-5 pll signals 2-7 pm0?m7 bits 8-8 port a 1-10 controlling 5-7 disabling 5-7 port a signals 2-10
q index-8 DSP56602 user? manual motorola port b gpio signals pb0?b7 2-13 pb10 2-14 pb11 2-15 pb12 2-15 pb13 2-16 pb14 2-16 pb15 2-17 pb8 2-13 pb9 2-14 port c control register (pcrc) 8-20 port c data register (pdrc) 8-22 port c direction register (prrc) 8-21 port c gpio signals pc0 2-18 pc1 2-18 pc2 2-19 pc3 2-19 pc4 2-20 pc5 2-20 port control bits (pc[3:0]) 6-5 port control bits (pc0?c5) 8-20 port d control register (pcrd) 8-20 port d data register (pdrd) 8-22 port d direction register (prrd) 8-21 port d gpio signals pd0 2-21 pd1 2-21 pd2 2-22 pd3 2-22 pd4 2-23 pd5 2-23 port data bits (pd[3:0]) 6-6 port direction control bits (pdc[3:0]) 6-5 port direction register (prr) 6-5 port enable bit (pen) 8-21 power & ground pins 2-5 power signals 2-5 ppl 1-9 predivider factor bits (pd0?d3) 4-17 predivider factor bits (pd4?d6) 4-20 prescale modulus select bits (pm0?m7) 8-8 prescaled clock enable bit (pce) 9-12 prescaler counter value bits (pc0?c13) 9-8 prescaler preload value bits (pl0?l13) 9-7 prescaler preload value bits (ps0?s1) 9-7 prescaler range bit (psr) 8-9 program address bus (pab) 1-12 program address generator (pag) 1-9 program control unit (pcu) 1-8 program counter register (pc) 1-9 program data bus (pdb) 1-11 program decode controller (pdc) 1-9 program interrupt controller (pic) 1-9 program memory 3-3 program patch logic (ppl) 1-9 prr register 6-5 bits 0??ort direction control bits (pdc) 6-5 reserved bits?its 4?5 6-5 prrc register 8-21 prrd register 8-21 ps0?s1 bits 9-7 psr bit 8-9 pstp bit 4-19 q quiet ground signal (gnd q ) 2-6 quiet power high voltage signal (v ccqh ) 2-5 quiet power low voltage signal (v ccql ) 2-5 r r/w bit 10-7 rd signal 2-11 , 5-4 rdf bit 8-18 re bit 8-12 read enable signal (rd ) 2-11 , 5-4 read/write command bit (r/w ) 10-7 receive data register (rx) 8-19 receive data register full bit (rdf) 8-18 receive data register full bit (rxdf) 7-26 receive enable bit (re) 8-12 receive exception interrupt enable bit (reie) 8-13 receive frame sync flag bit (rfs) 8-17 receive high register (rxh) 7-28 receive host request signal (hrrq ) 2-17 receive interrupt enable bit (rie) 8-12 receive last slot interrupt enable bit (rlie) 8-13 receive low register (rxl) 7-28 receive request enable bit (rreq) 7-23 receive shift register 8-19 receiver overrun error flag bit (roe) 8-18 register select bits (rs0?s4) 10-5 reie bit 8-13 reserved bits in bcr register bits 5?5 5-8 in crb register
s motorola DSP56602 user? manual index-9 bits 2? 8-10 in crc register bits 8?1 8-15 in hbar register bits 5?5 7-17 in hcr register bits 5?5 7-10 in hpc register bit 7 7-13 in hsr register bits 5?5 7-11 in icr register bit 6 7-25 in isr register bits 5? 7-27 in obcr register bits 12?5 10-14 in omr register bit 7, bit 13, bit 14 4-6 in oscr register bit 5, bits 8?3 10-9 in pcrc register bit 6, bits 8?5 8-21 in pcrd register bit 6, bits 8?5 8-21 in pcre register bits 4?5 6-5 in pctl1 register bit 8, bits 12?5 4-20 in pdre register bits 4?5 6-6 in prr register bits 4?5 6-5 in ssisr register bits 8?5 8-19 in tcsr register bit 3 9-13 in tpcr register bits 14?5 9-8 reset signal 2-8 reverse-carry adder 1-8 rfs bit 8-17 rie bit 8-12 rlie bit 8-13 roe bit 8-18 rreq bit 7-23 rs0?s4 bits 10-5 rw00?w01 bits 10-12 rw10?w11 bits 10-13 rx register 8-19 rxdf bit 7-26 rxh register 7-28 rxl register 7-28 s sample/preload instruction 11-9 sc register 1-9 sc0 signal 8-4 , 8-5 sc00 signal 2-18 sc01 signal 2-18 sc02 signal 2-19 sc1 signal 8-4 sc10 signal 2-21 sc11 signal 2-21 sc12 signal 2-22 scd0 bit 8-14 scd1 bit 8-14 scd2 bit 8-15 sck signal 8-5 sck0 signal 2-19 sck1 signal 2-22 sckd bit 8-15 sd bit 4-5 serial clock signal (sck) 8-5 serial control 0 direction bit (scd0) 8-14 serial control 0 signal (sc0) 8-4 , 8-5 serial control 1 direction bit (scd1) 8-14 serial control 1 signal (sc0) 8-4 serial control 2 direction bit (scd2) 8-15 serial input flag 0 bit (if0) 8-17 serial input flag 1 bit (if1) 8-17 serial output flag 0 bit (of0) 8-10 serial output flag 1 bit (of1) 8-10 serial protocol in once module 10-23 serial receive data signal (srd) 8-6 serial transmit data signal (std) 8-6 shfd bit 8-15 shift direction bit (shfd) 8-15 size register (sz) 1-9 software debug occurrence bit (swo) 10-8 sp 1-9 sr register 1-9 , 4-7 sram read access 5-5 write access 5-5 srd signal 8-6 srd0 signal 2-20 srd1 signal 2-23 ss 1-9 ssi 1-14
t index-10 DSP56602 user? manual motorola asynchronous mode 8-24 frame sync selection 8-25 operating mode selection 8-24 operating modes 8-22 shift direction selection 8-26 synchronous mode 8-24 ssi control register a (cra) 8-7 ssi mode select bit (mod) 8-14 ssi status register (ssisr) 8-16 ssi, gpio, and timers ground signal (gnd s ) 2-6 ssi, gpio, and timers power signal (v ccs ) 2-5 ssi0 serial clock signal (sck0) 2-19 serial control 0 signal (sc00) 2-18 serial control 1 signal (sc01) 2-18 serial control 2 signal (sc02) 2-19 serial receive data signal (srd0) 2-20 serial transmit data signal (std0) 2-20 signals 2-18 ssi0 signals 2-18 ssi1 serial clock signal (sck1) 2-22 serial control 0 signal (sc10) 2-21 serial control 1 signal (sc11) 2-21 serial control 2 signal (sc12) 2-22 serial receive data signal (srd1) 2-23 serial transmit data signal (std1) 2-23 signals 2-21 ssi1 signals 2-21 ssisr register 8-16 bit 0?erial input flag 0 bit (if0) 8-17 bit 1?erial input flag 1 bit (if1) 8-17 bit 2?ransmit frame sync flag bit (tfs) 8-17 bit 3?eceive frame sync flag bit (rfs) 8-17 bit 4?ransmitter underrun error flag bit (tue) 8-18 bit 5?eceiver overrun error flag bit (roe) 8-18 bit 6?ransmit data register empty bit (tde) 8-18 bit 7?eceive data register full bit (rdf) 8-18 reserved bits?its 8?5 8-19 stack counter register (sc) 1-9 stack pointer (sp) 1-9 status register (sr) 1-9 , 4-7 std signal 8-6 std0 signal 2-20 std1 signal 2-23 stop delay bit (sd) 4-5 stop processing state bit (pstp) 4-19 swo bit 10-8 syn bit 8-14 synchronous serial interface (ssi) 1-14 synchronous serial interface 0 signals 2-18 synchronous serial interface 0 signals (ssi0) 2-18 synchronous serial interface 1 signals 2-21 synchronous serial interface 1 signals (ssi1) 2-21 system stack (ss) 1-9 sz register 1-9 t tap 1-10 tap controller 11-6 tc0?c3 bits 9-10 tcf bit 9-12 tcie bit 9-9 tck pin 11-5 tck signal 2-26 tcpr register 9-9 tcsr register 9-9 bit 0?imer enable bit (te) 9-9 bit 1?imer overflow interrupt enable bit (toie) 9-9 bit 2?imer compare interrupt enable bit (tcie) 9-9 bits 4??imer control bits (tc0?c3) 9-10 bit 8?nverter bit (inv) 9-11 bit 9?imer reload mode bit (trm) 9-11 bit 10?irection bit (dir) 9-11 bit 11?ata input bit (di) 9-11 bit 12?ata output bit (do) 9-12 bit 13?imer overflow flag bit (tof) 9-12 bit 14?imer compare flag bit (tcf) 9-12 bit 15?rescaled clock enable bit (pce) 9-12 reserved bit?it 3 9-13 tde bit 8-18 tdi pin 11-5 tdi signal 2-26 tdo pin 11-5 tdo signal 2-26 te bit 8-11 , 9-9 teie bit 8-13 test access port (tap) 1-10 , 11-3 test clock input pin (tck) 11-5 test clock signal (tck) 2-26 test data input pin (tdi) 11-5
v motorola DSP56602 user? manual index-11 test data input signal (tdi) 2-26 test data output pin (tdo) 11-5 test data output signal (tdo) 2-26 test mode select input pin (tms) 11-5 test mode select signal (tms) 2-26 test reset input pin (trst ) 11-5 test reset signal (trst signal) 2-26 tfs bit 8-17 ti00 signal 2-25 ti02 signal 2-25 tie bit 8-12 time slot register (tsr) 8-20 timer 0 i/o signal (ti00) 2-25 timer 1 i/o signal (ti01) 2-25 timer 2 i/o signal (ti02) 2-25 timer architecture 9-4 timer compare flag bit (tcf) 9-12 timer compare interrupt enable bit (tcie) 9-9 timer compare register (tcpr) 9-9 timer control bits (tc0?c3) 9-10 timer control/status register (tcsr) 9-9 timer enable bit (te) 9-9 timer load register (tlr) 9-8 timer modes measurement modes 9-16 pwm mode 9-17 reserved modes 9-19 timer modes 9-14 watchdog modes 9-18 timer overflow flag bit (tof) 9-12 timer overflow interrupt enable bit (toie) 9-9 timer prescaler load register (tplr) 9-7 timer reload mode bit (trm) 9-11 tio1 signal 2-25 tlie bit 8-13 tlr register 9-8 tme bit 10-8 tms pin 11-5 tms signal 2-26 to bit 10-9 tof bit 9-12 toie bit 9-9 tpcr register bits 0?3?rescaler counter value bits (pc0?c13) 9-8 reserved bits?its 14?5 9-8 tplr register 9-7 bits 0?3?rescaler preload value bits (pl0?l13) 9-7 bits 14?5?rescaler source bits (ps0?s1) 9-7 trace buffer 10-21 trace mode enabling 10-18 in once module 10-15 trace mode enable bit (tme) 10-8 trace occurrence bit (to) 10-9 transmit data register (tx) 8-20 transmit data register empty bit (tde) 8-18 transmit data register empty bit (txde) 7-27 transmit enable bit (te) 8-11 transmit exception interrupt enable bit (teie) 8-13 transmit frame sync flag bit (tfs) 8-17 transmit high register (txh) 7-29 transmit host request signal (htrq ) 2-16 transmit interrupt enable bit (tie) 8-12 transmit last slot interrupt enable bit (tlie) 8-13 transmit low register (txl) 7-29 transmit request enable bit (treq) 7-23 transmit shift register 8-19 transmitter ready bit (trdy) 7-27 transmitter underrun error flag bit (tue) 8-18 trdy bit 7-27 treq bit 7-23 triple timer module 1-14 triple timer signals 2-25 trm bit 9-11 trst pin 11-5 trst signal 2-26 tsr register 8-20 tue bit 8-18 tx register 8-20 txde bit 7-27 txh register 7-29 txl register 7-29 v vba register 1-9 , 4-11 v cca signal 2-5 v ccc signal 2-5 v ccd signal 2-5 v cch signal 2-5 v ccp signal 2-5 v ccqh signal 2-5 v ccql signal 2-5 v ccs signal 2-5 vector base address register (vba) 1-9 , 4-11 w wl0?l1 bits 8-8
x index-12 DSP56602 user? manual motorola word length control bits (wl0?l1) 8-8 wr bit 4-6 wr signal 2-11 , 5-4 write enable signal (wr ) 2-11 , 5-4 x x data memory 3-4 x memory address bus (xab) 1-12 x memory data bus (xdb) 1-11 x memory expansion bus 1-11 xab 1-12 xdb 1-11 xtal disable bit (xtld) 4-19 xtal signal 2-7 xtld bit 4-19 xtlr bit 4-19 xy select bit (xy) 4-5 y y data memory 3-4 y memory address bus (yab) 1-12 y memory data bus (ydb) 1-12 y memory expansion bus 1-11 yab 1-12 ydb 1-12
overview signal/connection description memory maps core configuration external memory interface (port a) gpio host interface (hi08) synchronous serial interface triple timer module on-chip emulation module jtag port bootstrap program x i/o equates index programmer? reference 1 2 3 4 5 6 7 8 10 11 a b 9 d i bsdl listing c
overview signal/connection description memory maps core configuration external memory interface (port a) gpio host interface (hi08) synchronous serial interface triple timer module on-chip emulation module jtag port bootstrap program x i/o equates index programmer? reference 1 2 3 4 5 6 7 8 10 11 a b 9 d i bsdl listing c


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